Hamid Reza Zarandi - Amirkabir University of Technology

Educational Records

#

Degree/Major

University

City

Country

Graduation Date

1

Computer Engineering (PhD)

Sharif University of Technology

Tehran

IRAN

March 2007

2

Computer Engineering (BSc)

Sharif University of Technology

Tehran

IRAN

Sept. 2000

3

Computer Engineering (MSc)

Sharif University of Technology

Tehran

IRAN

Sept. 2002

Scientific & Industrial Experience

#

Responsibilities Titles

Name of Organization

Starting Date

Termination Date

1

Visiting researcher

University of California, Irvine, US

2

Visiting researcher

Passau University, Germany

3

Visiting researcher

INRIA research Institute, France

4

Visiting researcher

University of Bristol, UK

Research Interests

#

Title

Start date

1

Networks-On-Chip

2

Reliable System Design

3

Computer Architecture

4

Embedded Systems

Supervised PhD Theses

#

Thesis title

By

Date

1

A Fault Tolerant ReRAM-based Process-in-Memory Architecture for Neural Network Accelerators

Aniseh Dorostkar & Hamed Farbeh
Other Supervisor:

2026 Jan

2

Efficient approximate memristive in-memory computing for data intensive applications

Amir Mohammad Hajisadeghi Kahdooyeh
Other Supervisor: Mahmoud Momtazpoor

2025 Feb

Supervised MSc Theses

#

Thesis title

By

Date

1

Design and Implementation of a Blockchain Based on FPGA in IoT Devices

Mehri Ramazi Afoos

2024 Dec

2

Reducing network traffic of consensus algorithm in blockchain based on peer-to-peer networks using genetic algorithm

Murtada Almahdawi

2024 Dec

3

Proposing a Soft Error Tolerant Method for Crossbar-based Processing- in- ReRAM Architecture

Benyamin Khezli

2024 Sep

4

Proposing a Fault-Tolerant Method for Heart Arrhythmia Detection

Zahra Hasani

2024 Aug

5

Design and Implementation of an Efficient and Reliable Blockchain on NoC Architecture

Arman Gheysari

2023 Sep

6

Improvement of reliability testing of embedded systems software

Meysam Sharifzadeh Ardekani
Other Supervisor: Hamed Farbeh

2023 Jul

7

Design and Implementation of CNN Accelerator Based on 3D NoC Architecture

Mohammad Abbaszadeh

2023 Jul

8

Reliability Optimization of 3D-NoC Configuration with Cost and Delay Constraints

Hesam Abdolhosseini

2023 Mar

9

To Propose a Cost-Effective Method for Finding Minimal White-Box Test Cases to Guarantee Coverage in Embedded Softwares

Reyhaneh Soltanshah

2022 Oct

10

Fault tolerance improvement of IoT devices based on implementing redundancies on blockchain technology

Farhad Mofrad

2022 Sep

11

Fault Tolerance Evaluation of LoRa-based Devices in IoT and Proposing an Improvement Method

Seyede Fatemeh Anvari

2022 Sep

12

Vulnerability evaluation of LPWAN IoT protocol, NB-IoT, Using Fault Injection and Proposing an improvement method

Fatameh Khojasteh Dana

2022 Jun

13

Automatic Context-aware IoT Device Failure Detection in Smart Homes

Alireza Borhani

2021 Aug

14

An Approximate Computing method for Static and temporal Fault Tree Analysis

Navid Abbasnezhad Talebkhan
Other Supervisor: Saadat Pourmozafari

2021 Feb

15

An Approximate Computing method for Dynamic Fault Tree Analysis

Salar Hashemi Taheri
Other Supervisor: Saadat Pourmozafari

2019 Oct

16

A Cross-Layer Method to Tolerate Multiple Event Transients (METs) in Combinational Circuits

Amirmohammad Hajisadeghi Kahdooyeh

2018 Sep

17

To Present a Method For Tolerating Write Errors in STT-RAM Memories Considering Power Consumption

Saeed Seyedfaraji

2018 Sep

18

Soft Error Susceptibility Mitigation of RRAM-based Memory Arrays

Hossein Bardareh

2018 Feb

19

Tolerating Read Disturbances in RRAM Memories

Mohammadreza Nakhkash

2018 Feb

20

Reducing Vulnerability of STT- based Logic-in- Memory Adder Against Soft Errors

Javad Talafy

2018 Feb

21

Aging- aware task scheduling in MPSoC using knowledge from low abstraction- levels

Masoomeh Karami

2017 Mar

22

a robust aging sensor design against process variation

Parnian Shabani Kamran

2016 Sep

23

A Method to Reduce NBTI Effect in SRAM Cell

Vahid Amini

2016 Sep

24

Amethod to reduce Aging effect in a finfet Adder

Fatemeh Hosseini

2016 Sep

25

A Method To Tolerate NBTI In Digital Circuits

Maryam Ghane

2015 Dec

26

An improvement on Reduction of Silent Data Corruption error in CPUs

Sayed Ali Houri

2015 Aug

27

An Improved Wear-out Faults recovery in CMPs

Elham Kashefi

2015 Feb

28

a technique to increase reliability in memristor-based memories

Peiman Pour Momen

2014 Oct

29

adaptive Anomaly Detection caused by sensors in embeded systems

Fatemeh Ehsani Besheli

2014 Oct

30

a Multiple Soft Error Tolerant Method in Networks on Chip

Saeed Kohsari

2014 Apr

31

Improving Efficiency in Distributed Embedded Systems Based on WCAN with Power Control Constraints

Mohsen Seyyedi Saravi

2013 Nov

32

Accelerating fault tree analysis using stochastic logic implemented on H.W

Elham Cheshmikhanikhanghah

2013 Oct

33

An Adaptive Deadlock-Avoidance Routing Algorithm For Network on Chips

Kamran Nasiri

2013 Oct

34

A New Method for Anomaly Correction in Embedded Systems

Roghaye Mojarrad

2013 Oct

35

A Method to improve SDC detection coverage in CPUs

Fatame Eman Parast

2013 Oct

36

presenting a fault-tolerant technique against soft errors in many-core processors

Elnaz Ghods_e_vali

2012 Nov

37

proposing a new nethod to tolerate multiple faults in embedded systems with timing constraints

Mohammad Hadi Mottaghi Khezri

2012 Oct

38

evalution of soft error on rollback recoverymethod in embedded systems

Hossein Malaee Aghdam

2012 Oct

39

robustness assessment of reconfigurable network-on-chip against side-channel attachs

Shadan Shahdi

2012 Sep

40

performance evluation of wireless network-on-chip

Neda Tavakoli

2012 Sep

41

consideration of security in wired networks-on-chip

Faranak Jannati

2012 Sep

42

presenting a fault-aware application task mapping on CMPs regarding to communication energy

Fatemeh Khalili

2012 Sep

43

Presenting a fault-tolerant mechanism for network on chip with low performance penalty

Saleh Fakhrali

2012 Feb

44

Presenting a method to mitigate soft error effects in reconfigurable network-on-chips

Ronak Salamat

2012 Feb

45

Presenting and evaluating a technique for control- flow error recovery in multicore processors

Navid Khoshavi Najaf Abadi

2012 Jan

46

Fault-tolerant evaluations of buffering types and virtual buffers in network-on-chip routers

Farveh Saber Mahani

2011 Dec

47

Developing a run-time soft error recovery method for multicores

Hananeh Aliee

2011 Sep

48

Implementation of stide anomaly detection method in embedded systems

Hoda Ghabeli

2011 May

49

An anomaly detection technique in embedded systems to increase fault coverage

Mahroo Zandrahimi

2010 Dec

50

Design of computer networks for digital control system of power plants

Masoud Evazi

2010 Oct

51

Increasing in asynchronous circuit delay fault tolerance due to process variation

Mohsen Rajiasadabadi

2010 Sep

52

Dependability evaluation and improvement in CAN-based embedded systems

Saman Khoshbakht

2010 Jul

53

Design and evaluation of a structural method for dependability in SRAM-based FPGAs

Alireza Rohani

2010 Feb

54

A fault-tolerant routing technique in SRAM-based FPGAs

Somayeh Bahramnejad

2009 Dec

55

Simultaneous Management of Reliability, Performance and Power Consumption in Mixed-Criticality Multi-Core Systems Using Reinforcement Learning

Parnian Sagheb Haghighi

2025 Sep

56

Presenting a fault-tolerant accurate heart rate arrhythmia detector using ECG,ABP and pulse oximetry

Ali Modanlou

2025 Sep

57

Improving the Reliability of Task Offloading in Edge Computing Using Reinforcement

Fateme Hosseini

2025 Sep

58

Resilience enhancement of LoRa device used in gateway-based LoRaWAN against PSD and EMI

Faezeh Saghaei

2025 Mar

Books

#

Title

Author(s)

Publisher country

publication date

version

1

Nanoscale Memristor Device and Circuits Design

A.M. Hajisadeghi Kahdooyeh, J. Talafy, H.R. Zarandi

Britain

0

Journal Papers

1

H. Abdolhosseini, H.R. Zarandi, A. Gheysari, "Simultaneous Optimization of Network-on-Chip to Improve Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints", Journal of Supercomputing, 2025 Aug vol. 81, no. 13, pp.1-37, 2025.

2

F. Saghaei, H.R. Zarandi, M. Tavakoli Bazaz, "A Comprehensive Vulnerability Analysis of LoRaWAN-based Cyber-Physical Systems in the Presence of EMI and PSD Transient Faults", Scientia Iranica, 2025 Jul vol. 1, no. 1, pp.1-21, 2025.

3

A. Hajisadeghi Kahdooyeh, M. Ghane, H.R. Zarandi, "OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits", Analog Integrated Circuits and Signal Processing, 2025 Jun vol. 126, no. 18, pp.1-15, 2025.

4

A. Gheysari, H.R. Zarandi, "Security-Aware Optimization of PoW-based Blockchain Performance Using a Genetic Algorithm Approach", Sustainable Computing-Informatics and Systems, 2025 Jun vol. 48, no. 101232, pp.1-14, 2025.

5

A. Zarei, H.R. Zarandi, A.M. Hajisadeghi Kahdooyeh, "Analysis and Hardening of Combinational Standard Cells Against Transient Faults Using Device-Level Simulations", Scientia Iranica, 2025 Jun vol. 1, no. 1, pp.1-16, 2025.

6

F. Khojasteh Dana, S.F. Anvari, H.R. Zarandi, "A reliability framework for NB-IoT devices: Addressing transient faults and silent data corruptions", Computers and Electrical Engineering, 2025 May vol. 124, no. 2, pp.110405-, 2025.

7

A.M. Hajisadeghi Kahdooyeh, H.R. Zarandi, M. Momtazpoor, "Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM", Aeu-International Journal of Electronics and Communications, 2024 Nov vol. 190C, no. 155614, pp.1-14, 2024.

8

A. Dorostkar, H. Farbeh, H.R. Zarandi, "An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators", Ieee Transactions On Reliability, 2024 Jun vol. 1, no. 1, pp.1-15, 2024.

9

A.M. Hajisadeghi Kahdooyeh, M. Momtazpoor, H.R. Zarandi, "Approx-IMC: A General-Purpose Approximate Digital In-Memory Computing Framework Based on STT-MRAM", Future Generation Computer Systems-The International Journal of Escience, 2024 May vol. 160, no. 1, pp.40-53, 2024.

10

A. Hajisadeghi Kahdooyeh, H.R. Zarandi, "CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics", Microprocessors and Microsystems, 2021 Sep vol. 85, no. 104282, , 2021.

11

A.R. Tajary, H.R. Zarandi, Nader Bagherzadeh, "IRHT: An SDC Detection and Recovery Architecture Based on Value Locality of Instruction Binary Codes", Microprocessors and Microsystems, 2020 Jun vol. 77, no. 0, pp.1-13, 2020.

12

J. Talafy, F. Zokaee, H.R. Zarandi, Nader Bagherzadeh, "A High Performance, Multi-Bit Output Logic-in-Memory Adder", Ieee Transactions On Emerging Topics In Computing, 2020 Mar vol. 0, no. 0, pp.1-11, 2020.

13

S. Seyedfaraji, A. Hajisadeghi Kahdooyeh, J. Talafy, H.R. Zarandi, "DYSCO: DYnamic Stepper Current InjectOr to Improve Write Performance in STT-RAM Memories", Microprocessors and Microsystems, 2019 Dec vol. 73, no. 1, pp.102963-102974, 2019.

14

A. Abdi, Alain Girault, H.R. Zarandi, "ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores", Ieee Transactions On Parallel and Distributed Systems, 2019 Mar vol. 0, no. 0, pp.1-18, 2019.

15

A. Abdi, H.R. Zarandi, "A Meta Heuristic-based Task Scheduling and Mapping Method to Optimize Main Design Challenges of Heterogeneous Multiprocessor Embedded Systems", Microelectronics Journal, 2019 Mar vol. 87, no. 1, pp.1-11, 2019.

16

Shahab Shoar, Farnad Nasirzadeh, H.R. Zarandi, "Quantitative assessment of risks on construction projects using fault tree analysis with hybrid uncertainties", Construction Innovation-England, 2018 Nov vol. 19, no. 1, pp.48-70, 2018.

17

A. Abdi, M. Karami, H.R. Zarandi, "Lifetime Reliability Enhancement in Multiprocessor Systems Through a Fine-Grained System-level Approach", Journal of Circuits Systems and Computers, 2018 Oct vol. 28, no. 11, pp.195019-195039, 2018.

18

F. Zokaee, H.R. Zarandi, Lei Jiang, "AligneR: A Process-In-Memory Architecture for Short Read Alignment in ReRAMs", Ieee Computer Architecture Letters, 2018 Jul vol. 14, no. 8, pp.1-4, 2018.

19

M. Karami, A. Abdi, H.R. Zarandi, "A Cross-Layer Aging-aware Task Scheduling Approach on Multiprocessor Embedded Systems", Microelectronics Reliability, 2018 Apr vol. 85C, no. 1, pp.190-197, 2018.

20

A. Abdi, H.R. Zarandi, "HYSTERY: A Hybrid Scheduling and Mapping Approach to Optimize Temperature, Energy Consumption and Lifetime Reliability of Heterogeneous Multiprocessor Systems", Journal of Supercomputing, 2018 Jan vol. 0, no. 0, , 2018.

21

R. Mojarrad, H.R. Zarandi, "Comparison and Analysis of Three Anomaly Correction Methods in Embedded Systems", Scientia Iranica, 2017 Feb vol. 1, no. 1, pp.1-10, 2017.

22

Shahab Shoar, H.R. Zarandi, Farnad Nasirzadeh, E. Cheshmikhanikhanghah, "Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk", Quality and Reliability Engineering International, 2016 Nov vol. 0, no. 12, pp.1-19, 2016.

23

A. Tajary, H.R. Zarandi, "Using Instruction Result Locality and Re-Execution to Mitigate Silent Data Corruptions", Microelectronics Reliability, 2016 Mar vol. 0, no. 0, pp.1-13, 2016.

24

S. Fakhrali, H.R. Zarandi, "Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip", Journal of Circuits Systems and Computers, 2016 Mar vol. 25, no. 6, pp.1-15, 2016.

25

M. Maghsoudloo, H.R. Zarandi, "Design space exploration of non-uniform cache access for soft-error vulnerability mitigation", Microelectronics Reliability, 2015 Sep vol. 0, no. 0, , 2015.

26

E. Cheshmikhanikhanghah, H.R. Zarandi, "Probabilistic Analysis of Dynamic and Temporal Fault Trees Using Accurate Stochastic Logic Gates", Microelectronics Reliability, 2015 Jun vol. 1, no. 1, pp.1-1, 2015.

27

S. Fakhrali, H.R. Zarandi, "FXY: A Hierarchical Routing Algorithm to Balance Performance and Fault Tolerance in Networks-On-Chip", Journal of Circuits Systems and Computers, 2014 Jul vol. 23, no. 10, pp.1-23, 2014.

28

M. Maghsoudloo, H.R. Zarandi, "Cache Vulnerability Mitigation Using an Adaptive Cache Coherence Protocol", Journal of Supercomputing, 2014 Feb vol. 1, no. 1, pp.1-1, 2014.

29

M.H. Mottaghi Khezri, H.R. Zarandi, "DFTS: A Dynamic Fault-Tolerant Scheduling for Real-Time Tasks in Multicore Processors", Microprocessors and Microsystems, 2014 Feb vol. 38, no. 1, pp.88-97, 2014.

30

M. Maghsoudloo, H.R. Zarandi, "Reliability Improvement in Private Non-Uniform Cache Architecture using Two Enhanced Structures for Coherence Protocols and Replacement Policies", Microprocessors and Microsystems, 2013 Dec vol. 38, no. 6, pp.552-564, 2013.

31

Hamid Sarbazi-azad, H.R. Zarandi, Mahdi Fazeli, "A parallel clustering algorithm on the star graph and its performance", Mathematical and Computer Modelling, 2013 Aug vol. 58, no. 0, pp.880-891, 2013.

32

F. Khalili, H.R. Zarandi, "A Fault-Tolerant Core Mapping Technique in Networks-on-Chip", Iet Computers and Digital Techniques, 2013 Jun vol. 1, no. 1, pp.1-1, 2013.

33

H. Aliee, H.R. Zarandi, "A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays", Ieee Transactions On Reliability, 2013 Jan vol. 61, no. 4, pp.1-1, 2013.

34

M. Maghsoudloo, H.R. Zarandi, N. Khoshavi Najaf Abadi, "An Efficient Adaptive Software-Implemented Technique to Detect Control-Flow Errors in Multi-Core Architectures", Microelectronics Reliability, 2012 Nov vol. 52, no. 11, pp.2812-2828, 2012.

35

M. Maghsoudloo, H.R. Zarandi, N. Khoshavi Najaf Abadi, "On-line Control Flow Error Detection and Correction Based on Monitoring both Data-flow and Control-flow Graphs", Journal On Computer Science and Engineering, 2012 Apr vol. 10, no. 0, pp.10-19, 2012.

36

M. Zandrahimi, H.R. Zarandi, M.H. Mottaghi Khezri, "Two effective methods to detect anomalies in embedded systems", Microelectronics Journal, 2012 Jan vol. 43, no. 1, pp.77-87, 2012.

37

S. Bahramnejad, H.R. Zarandi, "Mitigation of soft errors in SRAM-based FPGAs using CAD tools", Computers and Electrical Engineering, 2011 Nov vol. 37, no. 6, pp.1019-1031, 2011.

38

S. Bahramnejad, H.R. Zarandi, "An adaptive method to tolerate soft errors in SRAM-based FPGAs", Scientia Iranica, 2011 Sep vol. 16, no. 1, pp.1-10, 2011.

39

M. Kishanifarahani, H.R. Zarandi, H. Pedram, A.R. Tajary, M. Raji Asad Abadi, B. Ghavami, "HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors", Design Automation For Embedded Systems, 2011 May vol. 16, no. 1, pp.1-22, 2011.

40

P. Mohammadi Yaghini, A. Eghbal, H. Pedram, H.R. Zarandi, "Investigation of Transient Fault Effects in Synchronous and Asynchronous Network on Chip Router Reliability", Journal of Systems Architecture, 2011 Jan vol. 57, no. 10, pp.61-68, 2011.

41

H. Ebrahimi, M. Saheb Zamani, H.R. Zarandi, "Mitigating Soft Errors in SRAM-Based FPGAs by Decoding Configuration Bits in Switch Boxes", Microelectronics Journal, 2011 Jan vol. 42, no. 1, pp.12-20, 2011.

42

Pedram Rajabzadeh, Hamid Sarbaziazad, H.R. Zarandi, Ebrahim Khodaie, Hashem Hashemi Najafabadi, Mohamed Ouldkhaoua, "Performance Modeling of n-Dimensional Mesh Networks", Performance Evaluation, 2010 Dec vol. 67, no. 12, pp.1304-1323, 2010.

43

A. Eghbal, H. Pedram, P. Mohammadi Yaghini, H.R. Zarandi, "Designing a Fault-tolerant NoC Router Architecture Respecting Fault Effects", International Journal of Electronics, 2010 Oct vol. 97, no. 10, pp.1181-1192, 2010.

44

A. Rohani, H.R. Zarandi, "Two Effective Methods to Mitigate Soft Error Effects in SRAM-based FPGAs", Microelectronics Reliability, 2010 Aug vol. 50, no. 8, pp.1171-1180, 2010.

45

M. Rajiasadabadi, B. Ghavami, H. Pedram, H.R. Zarandi, "Process Variation Aware Performance Analysis of Asynchronous Circuits", Elsevier Journal of Microelectronics, 2010 Mar vol. 41, no. 2, , 2010.

46

H. Aliee, H.R. Zarandi, P. Mohammadi Yaghini, "K2Router: A Low-Power and High-Performance Router Design for Networks-On-Chip", Journal On Computer Science and Engineering, 2009 Mar vol. 7, no. 2, pp.8-23, 2009.

47

H.R. Zarandi, "A SEU-protected cache memory-based on variable associativity of sets", Reliability Engineering and System Safety, 2007 Nov vol. , no. 92, , 2007.

48

H.R. Zarandi, "Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs", Microelectronics Reliability, 2007 Mar vol. , no. 0, , 2007.

49

H.R. Zarandi, "Hierchical Set -Associate Cache For High -Performance and Low -Energy Architecture", Journal of Circuits Systems and Computers, 2006 Jun vol. , no. 6, , 2006.

50

H.R. Zarandi, "A fault-tolerant cache architecture based on binary set partitioning", Microelectronics Reliability, 2006 Jan vol. , no. 46, , 2006.

51

H.R. Zarandi, "Hierarchical Binary Set Partitioning in Cache Memories", Journal of Supercomputing, 2005 Dec vol. , no. 31, , 2005.

Awards & Honors

#

title

Date

1

Distinguished professor, Dept. of Computer Engineering, Amirkabir Univ. of Technology

2014

Professional Memberships

#

Professional memberships

Explanations

1

Head of IoT Center of Excellence.

2

Member of Cyber-Physical Systems Society of Iran

3

Member of Computer Society of Iran

4

Member of IEEE

5

Chair of DADS Research Laboratory

Taught Courses

#

Course title

Description

Headlines

Date

1

Fault-Tolerant System Design

4051

2

Computer Architecture

Computer architecture

4042

3

Test and Testability

4042

4

(Dependable Systems Design)

4041

5

Operating Systems

4041

6

Computer Architecture

4041

7

(Testing and Testable System Design)

4032

8

Operating Systems

4032

9

Computer Architecture

4032

Inventions/Patents

#

Invention title

Reg. number

Country

contributers

Reg. date

Exp. date

1

A method to detect Byzantine faults in systems-on-chip (SoCs) using blockchain, consensus algorithms, and a new proposed consensus algorithm.

2024/06/1

-

2

An NBTI mitigation method to eliminate critical internal nodes in digital circuits

2023/09/1

2038/01/19