MEHDI SEDIGHI - Amirkabir University of Technology

Supervised MSc Theses

#

Thesis title

By

Date

1

Design and implementation of a multi-parameter platform for intelligent management of buildings based on embedded systems

MIR SAEID ZENOZI

2024 Aug

2

Design and implementation of a multi parameter platform for intelligent building management using reinforcement learning

VIDA BARZEGARAN

2024 Aug

3

Quantum Circuit Synthesis Using Reinforcement Learning Based on MCTS

FAEZEH HEMATZADEH & MORTEZA SAHEB ZAMANI
Other Supervisor:

2024 Aug

4

Quantum Circuit Synthesis Considering Interconnections of Qubits

SEYYEDMOHAMMADSAEED FATTAHI
Other Supervisor: MORTEZA SAHEB ZAMANI

2023 Sep

5

Low-Power Hardware Accelerator Design on FPGA Devices for Artificial Intelligence Approximate Applications

NADIA SOHRABI

2023 Jun

6

joint Admission Control and Load Distribution in Cloud Datacenters for Profit Maximization Considering Dynamic Energy Consumption and Cooling Costs

AMIRHOSSEIN SHARIATIKIA
Other Supervisor: BAHADOR BAKHSHI SARESKANROOD

2023 Jun

7

Providing secure IoT architecture based on distributed solution

MUHAMMAD SADEGH ZARRABI

2021 Jan

8

A Technique for Partitioning of Circuit in Scalable Quantum Computers

BAHARE JALILI & MORTEZA SAHEB ZAMANI
Other Supervisor:

2020 Aug

9

Implementing decentralize file system on mobile cloud computing enviroment

MITRA HOJATIFARD

2019 Jul

10

Synthesizing Approximate Decimal Fixed- point Arithmetic on a Reconfigurable Integer architecture

ZAHRA JAVADI TABRIZI

2019 Jun

11

AFlexible Platform to Design Real Time,Embedded Driver Assistant Systeems

ALI KAMALI

2018 Feb

12

High Level Synthesis of Decimal Arithmetic Circuits on Reconfigurable Architectures

MASUME NAJM

2018 Feb

13

Power Management and Resource Allocation in Mobile Nodes Network

SOHRAB MORTAZAVI GHALAATI

2017 Jul

14

MCC Enhancement Using D2D Communication

REZA GHOLAMI

2017 Jul

15

FaulT-tolerant quantum circuit synthesis

SOUDABE MOHAMADZADE

2017 Jan

16

A Reconfigurable Decimal Multiplier Desing and Implementation

MAHSA RAHMANI

2016 Oct

17

Simulation Of Quantum Circuits Using GPU

ARMAN GOUDARZI

2016 Jul

18

An Improved Reconfigurable Architecture For Arithmetic Units

VAHID HOJJATI ZADEH

2016 May

19

Design and implementation of an embedded system to detect driver drowsiness based on eye movements and ECU signals

EHSAN RAZZAZI

2015 Sep

20

Optimization of Arithmetic Circuits Based on High Level Description

FOROOGH HADDADI

2014 Oct

21

A hard real-time algorithm to detect driver drowsiness based on eye movements and ECU signals

REZA NARIMANI

2014 Oct

22

Task Scheduling and Resource Assignment in a Grid of Embeded Systems

REZVAN NANKALI

2013 Dec

23

quantum circuit synthesis using an extended library with TOFFOLI 3-qubit gate

SOMAYYEH MEHRABADI

2013 Nov

24

a method to parallel run application programs on an smart phones network

SALEH MEHDIKHANI

2013 Oct

25

Scheduling and Routing of Quantum Circuits Based on 3-qubit Gates in Ion-Trp Technology

FARANAK ADINEHZADEH

2013 Oct

26

reducing static power in caches for chip multiprocessors (CMPs)by considering perfomance

ELHAM SHIRKHANI

2013 Feb

27

accelerating PHD algorithm using parallel homogeneous artificial neural networks implementation on a GPU

DELASA AGHAMIRZAIE

2011 Oct

28

reducing execution time in fault tolerant quantum circuits

ZAHRA NABIZADEH.SHAHREBABAK

2011 Oct

29

a hierarchical layout generation method for quantum circuits in ion trap technology

MINA CHOOKHACHI ZADEH MOGHADAM

2011 Oct

30

automated implementation of quantum circuits on QFPGA for emulation

MOSTAFA HEYDARZADEHKALHRODI

2011 Feb

31

simulation of quantum circuits to reduce computation time and memory usage

AFSHAR KAKAEI

2011 Feb

32

analysis and comparison of models of computation in embedded systems in terms of fault- tolerance

MARMAR HOMAYOUNMEHR

2010 Oct

33

Introducing an adaptive algorithm for dynamic bandwidth allocation in EPON Access Networks

ARIAN MAGHAZE

2010 Jan

34

extending a verification language for designing reliable systems

HOSSEIN ATASHI

2010 Jan

35

A WiMAX-compatible enhancement of EPON for usage in access layer of network

MEHDI HAROUNABADI

2009 Dec

36

hardware implementation of a javaVirtual machine over a riscprocessor

MOHAMMAD ERFAN KHAZAEE

2009 May

37

hardware/software codesign considering reconfigurability and its application in implementing EFM

AIDA VOSOUGHI

2008 Nov

38

Proposing a new method for converting an irreversible circuit to a reversible circuit with the aim of reducing the cost of the synthesized circuit

ZAHRA SASANIAN

2008 Oct

39

ENHANCEMENT OF SPECIAL PURPOSE PROCESSORS VIA DYNAMIC RECONFIGURATION

HAMED PISHVAYAZDI

2008 Feb

40

AN IMPROVED CORE-COPRROCESSOR ARCHITECTURE FOR A MIPS PROCESSOR

MANSOUR SHAHIDI

2008 Feb

41

A NEW IMPROVED ALGORITHM FOR AUTOMATIC ASE INSTRUCTION GENERATION FOR A RISC PROCESSOR

RABEH RAVANIFARD

2007 Dec

42

NOC QOS ANALYSIS FROM ARCHITECTURAL PERSPECTIVE

MOHAMAD MOIENI JAHROMI

2007 Feb

43

AN APPROACH TO IMPROVE QOS IN NOCS USING RESOURCE MANAGEMENT IN ROUTERS

MAHBOOBEH SHARIAT

2007 Feb

44

DESIGN AND IMPLEMENTATION LINK LAYER OF HOME PNA IN BEHAVIORAL LEVEL FOR PERFORMANCE IMPROVEMENT

MOHAMAD KHALILI DARMANI

2007 Jan

45

Autonomous IoT Configuration Process Using eSIM over IoT-SAFE protocol

MOHAMMAD MAHDI NEMATI HARAVANI

2026 May

46

Regional Building Management System Using NB-LOT

ZAHRA TORKKOJURI

2025 Sep

47

Quantum Circuit Partitiong Quality Prediction for Implementation on Distributed Quantum Computers

MOHAMMAD RAMEZANI & MORTEZA SAHEB ZAMANI
Other Supervisor:

2025 Sep

48

multiplication operations speedup using ReRAM

NARJES MOHAMMADNEZHAD

2025 Oct

Books

#

Title

Author(s)

Publisher country

publication date

version

1

Digital Integrated Circuits Electronics

M. Sedighi, Ali Valizadeh

Iran

1

Journal Papers

1

Eesa Nikahd, M. Saheb Zamani, M. Sedighi, "Low-overhead code concatenation approaches for universal quantum computation", Quantum Information Processing, 2023 Jan vol. 22, no. 1, pp.79-102, 2023.

2

M.H. Mottaghi Khezri, M. Sedighi, M. Saheb Zamani, "FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects", Ieee Transactions On Computers, 2021 Nov vol. 71, no. 11, pp.1-1, 2021.

3

E. Nikahd, Naser Mohammadzadeh, M. Sedighi, M. Saheb Zamani, "Automated window-based partitioning of quantum circuits", Physica Scripta, 2021 Mar vol. 96, no. 3, pp.1-19, 2021.

4

A. Bavafatoosi, M. Sedighi, "FERMAT: FPGA energy reduction method by approximation theory", Journal of Supercomputing, 2021 Feb vol. 1, no. 1, pp.1-1, 2021.

5

M. Arabzadeh, M. Sedighi, M. Saheb Zamani, Sayed-amir Marashi, "A system architecture for parallel analysis of flux-balanced metabolic pathways", Computational Biology and Chemistry, 2020 Jun vol. 88, no. 107309, pp.1-15, 2020.

6

B. Zolfaghari, M. Sedighi, M. Fallah, "Designing programmable parallel LFSR using parallel prefix trees", Journal of Engineering Research, 2019 Oct vol. 7, no. 3, pp.105-122, 2019.

7

M.H. Mottaghi Khezri, M. Sedighi, M. Saheb Zamani, "Aging Mitigation in FPGAs Considering Delay, Power and Temperature", Ieee Transactions On Reliability, 2019 Jun vol. 68, no. 2, , 2019.

8

M. Eslamy, Mahboobeh Houshmand, M. Saheb Zamani, M. Sedighi, "Optimization of One-Way Quantum Computation Measurement Patterns", International Journal of Theoretical Physics, 2018 Nov vol. 57, no. 11, pp.3296-3317, 2018.

9

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, Sayed-amir Marashi, "A graph-based approach to analyze flux-balanced pathways in metabolic networks", Biosystems, 2018 Jan vol. 165, no. 0, pp.40-51, 2018.

10

E. Nikahd, M. Sedighi, M. Saheb Zamani, "Nonuniform code concatenation for universal fault-tolerant quantum computing", Physical Review A, 2017 Sep vol. 96, no. 3, pp.32337-32342, 2017.

11

S. Emami, M. Sedighi, "An optimized reconfigurable architecture for hardware implementation of decimal arithmetic", Computers and Electrical Engineering, 2017 Aug vol. 63, no. 0, pp.18-29, 2017.

12

M. Houshmand Kaffashian, M. Sedighi, M. Saheb Zamani, K. Marjoei, "Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics", Acm Journal On Emerging Technologies In Computing Systems, 2017 May vol. 13, no. 4, , 2017.

13

B. Zolfaghari, M. Fallah, M. Sedighi, "S-Restricted Compositions revisited", Discrete Mathematics and Theoretical Computer Science, 2017 Apr vol. 19, no. 1, pp.1-19, 2017.

14

M. Eslamy, M. Saheb Zamani, M. Sedighi, Mahboubeh Hooshmand Kaffashian, "Optimizing Quantum Circuits Using One-Way Quantum Computation based on pattern Geometry", , 2017 Feb vol. 14, no. 4, pp.286-298, 2017.

15

K. Marjoei, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "Quantum-Logic Synthesis Using Improved Block-Based Approach", Iranian Journal of Electrical and Computer Engineering, 2017 Jan vol. 14, no. 3, pp.239-248, 2017.

16

Mahnaz Asgharpour, M. Sedighi, Mohammad Reza Jahed Motlagh, "A study on a new bifurcation parameter in a modified Huber-Braun model", Tehnicki Vjesnik-Technical Gazette, 2017 Jan vol. 24, no. 2, pp.379-384, 2017.

17

S. Emami, M. Sedighi, "The Effect of Granularity on The Design of Decimal Arithmetic Reconfigurable Units", Iranian Journal of Electrical and Computer Engineering, 2016 Nov vol. 14, no. 4, pp.1-8, 2016.

18

S. Emami, M. Sedighi, "Exploring Reconfigurability Options Among Decimal Adders", Journal On Computer Science and Engineering, 2016 Oct vol. 13, no. 2, pp.32-41, 2016.

19

M. Rahmani, M. Sedighi, "A Reconfigurable Pipeline Decimal Multiplier", Journal On Computer Science and Engineering, 2016 Oct vol. 13, no. 1, pp.14-23, 2016.

20

M. Arabzadeh, M. Houshmand Kaffashian, M. Sedighi, M. Saheb Zamani, "Quantum-Logic Synthesis of Hermitian Gates", Acm Journal On Emerging Technologies In Computing Systems, 2015 Dec vol. 12, no. 4, , 2015.

21

E. Nikahd, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "One-Way Quantum Computer Simulation", Microprocessors and Microsystems, 2015 Mar vol. 39, no. 3, pp.210-222, 2015.

22

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, M. Arabzadeh, "Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates", Acm Journal On Emerging Technologies In Computing Systems, 2014 Dec vol. 11, no. 3, pp.1-10, 2014.

23

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, M.H. Samavatian, "Automatic translation of quantum circuits to optimized one-way quantum computation patterns", Quantum Information Processing, 2014 Aug vol. 13, no. 9, pp.1-20, 2014.

24

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, Monireh Houshmand, "Ga-based approach to find the stabilizers of a given sub-space", Genetic Programming and Evolvable Machines, 2014 May vol. 1, no. 1, pp.1-1, 2014.

25

N. Mohamadzade, M. Saheb Zamani, M. Sedighi, "Quantum Circuit Physical Design Methodology with Emphasis on Physical Synthesis", Quantum Information Processing, 2013 Nov vol. , no. 0, pp.1-21, 2013.

26

M. Yazdani, M. Saheb Zamani, M. Sedighi, "A Quantum Physical Design Flow Using ILP and Graph Drawing", Quantum Information Processing, 2013 Jun vol. 12, no. 7, pp.1-28, 2013.

27

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, M. Saeedi, "Depth-optimized reversible circuit synthesis", Quantum Information Processing, 2012 Sep vol. 12, no. 4, pp.1677-1699, 2012.

28

N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Gate Location Changing: An Optimization Technique for Quantum Circuits", International Journal of Quantum Information, 2012 Mar vol. 10, no. 3, pp.1-20, 2012.

29

M. Saeedi, M. Arabzadeh, M. Saheb Zamani, M. Sedighi, "Block-Based Quantum-Logic Synthesis", Quantum Information and Computation, 2011 Mar vol. 11, no. 0, pp.262-277, 2011.

30

M. Saeedi, M. Saheb Zamani, M. Sedighi, Z. Sasanian, "Reversible Circuit Synthesis Using a Cycle-Based Approach", Acm Journal On Emerging Technologies In Computing Systems, 2010 Dec vol. 6, no. 4, , 2010.

31

N. Mohamadzade, M. Saheb Zamani, M. Sedighi, "Auxiliary Qubit Selection: A Physical Synthesis Technique for Quantum Circuits", Quantum Information Processing, 2010 Jun vol. 9, no. 6, pp.1-16, 2010.

32

N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Quantum Physical Synthesis:Improving Physical Design by Netlist Modifications", Microelectronics Journal, 2010 Mar vol. 41, no. 4, , 2010.

33

M. Sedighi, S. Farrokhi, "GALS System Optimization Using Retiming Concept", Ieice Electronics Express, 2010 Feb vol. 7, no. 3, pp.209-215, 2010.

34

M. Saeedi, M. Sedighi, M. Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Synthesis", , 2009 Dec vol. , no. 0, , 2009.

35

M. Saeedi, N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Systhesis", International Journal of Physics, 2009 Feb vol. , no. 2, , 2009.

36

M. Saeedi, M. Sedighi, M. Saheb Zamani, "Synthesis of Reversible Circuits Using A Moving Forward Strategy", Ieice Electronics Express, 2008 Aug vol. , no. 17, , 2008.

37

F. Mehdipour, H. Noori, M. Saheb Zamani, T. Murakami, M. Sedighi, "Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit", , 2006 Oct vol. 0, no. 4096, , 2006.

38

F. Mehdipour, H. Noori, M. Saheb Zamani, T. Murakami, M. Sedighi, "An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Intructions on a Reconfigurable Functional Unit", , 2006 Aug vol. 0, no. 4186, , 2006.

39

F. Mehdipour, M. Saheb Zamani, M. Sedighi, "An Integrated Temporal Partitioning and Physical Design Framework for Static Compilation of Reconfigurable Computing Systems", Microprocessors and Microsystems, 2006 Jan vol. , no. 30, , 2006.

Conference Papers

1

S. Mohamadzade, M. Sedighi, M. Saheb Zamani, "An efficient and exact synthesis of n-qubit diagonal ring gates into Clifford and T gates,", 26th Iranian Conference on Electrical Engineering, May 2018.

2

M. Bagheri, S. Mortazavi Ghalaati, R. Gholami, M. Sedighi, "Location-Based Scheduling: An Approach To Address Challenges of Big Data and Mobile Cloud Computing,", International Symposium on Telecommunications, Sep 2016.

3

M. Eslamy, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "Geometry-Based Signal Shifting of One-Way Quantum Computation Measurement Patterns,", Iranian Conference on Electrical Engineering, May 2016.

4

E. Nikahd, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "GOWQS: Graph-Based One-Way Quantum Computation Simulator,", Iranian Conference on Electrical Engineering, May 2016.

5

M. Sedighi, F. Haddadi, S. Emami, Mahya Saffarpour, "A heuristic algorithm for high level synthesis of decimal arithmetic circuits using systemc,", 10th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) 2015, Apr 2015.

6

F. Adinehzadeh, N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Proposing an Approach for Scheduling and Routing of Quantum Circuits with Toffoli Gates in Ion-Trap Technology,", 22nd Iranian Conference on Electrical Engineering, May 2014.

7

M. Chookhachi Zadeh Moghadam, N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "A Hierarchical Layout Generation Method for Quantum Circuits,", International Symposium on Computer Architecture and Digital Systems (CADS'13), Oct 2013.

8

Z. Nabizadeh.shahrebabak, M. Sedighi, M. Saheb Zamani, "Simultaneous Improvement of Area, Delay, and Fault Tolerance in Quantum Circuits,", International Symposium on Computer Architecture and Digital Systems (CADS'13), Oct 2013.

9

M. Harounabadi, M. Sedighi, "A Fast Response Dynamic Bandwidth Allocation Algorithm for a Converged EPON and WiMAX Network,", The Sixth International Symposium on Telecommunications (IST2012), Nov 2012.

10

E. Nikahd, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "OWQS: One-Way Quantum Computation Simulator,", IEEE Euromicro Conference on Digital System Design (DSD'12), Sep 2012.

11

M. Houshmand Kaffashian, M.H. Samavatian, M. Saheb Zamani, M. Sedighi, "Extracting One-way Quantum Computation Patterns from Quantum Circuits,", International Symposium on Computer Architecture and Digital Systems (CADS'12), May 2012.

12

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, M. Saeedi, "Logical-Depth-Oriented Reversible Logic Synthesis,", International Workshop on Logic Synthesis (IWLS'11), Jun 2011.

13

, M. Saheb Zamani, M. Sedighi, "Improving latency of quantum circuits by gate exchanging,", Aug 2009.

14

Z. Sasanian, M. Sedighi, M. Saheb Zamani, "A Cycle Based Synthesis Algorithm for Reversible logic,", Jan 2009.

15

M. Saeedi, , M. Sedighi, M. Saheb Zamani, "Performance and timing yield enhancement using highway on chip planning,", Sep 2008.

16

M. Saheb Zamani, M. Taajobian, M. Sedighi, "An efficient non tree clock routing algorithm for reducing delay uncertainty,", Sep 2008.

17

M. Mirsaeedi, M. Saheb Zamani, M. Sedighi, "Multi objective statistical yield enhancement using evolutionary algorithm,", Sep 2008.

18

E. Khish Ardestani Zadeh, M. Saheb Zamani, M. Sedighi, "A fast transormation based synthesis algorithm for reversible circuits,", Sep 2008.

19

, M. Saeedi, M. Saheb Zamani, M. Sedighi, "FPGA based circuit model emulation of quantum algorithms,", Apr 2008.

20

M. Saeedi, M. Saheb Zamani, M. Sedighi, "Moving forward: a non search based synthesis method toward efficient CNOT based quantum circuit synthesis algorithm,", Jan 2008.

21

M. Saeedi, M. Sedighi, M. Saheb Zamani, "A novel synthesis algorithm for reversible circuits,", Nov 2007.

22

S. Farrokhi, M. Zamani, H. Pedram, M. Sedighi, "Asynchronous behavior relared retiming in gated- clock gals systems,", Sep 2007.

23

M. Saeedi, M. Saheb Zamani, M. Sedighi, "Algebraic characterization of CNOT- based quantum circuits with its applications on logic synthesis,", Aug 2007.

24

M. Saeedi, M. Saheb Zamani, M. Sedighi, "On the behavior of substitution based reversible circuit synthesis algorithms: investigation and improvement,", May 2007.

25

M. Saeedi, M. Sedighi, M. Saheb Zamani, "A new methodology for quantum circuit synthesis CNOT based circuits as an example,", May 2007.

26

E. Khish Ardestani Zadeh, S. Pourmozafari, M. Sedighi, "A Processing element architecture for hybrid video coding,", Nov 2006.

27

F. Mehdipour, M. Saheb Zamani, M. Sedighi, H. Noori, "GifT A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs,", Jun 2006.

28

E. Khish Ardestani Zadeh, S. Pourmozafari, M. Sedighi, "System-level Design of a Processing Element for Hybrid Video Coding,", Apr 2006.

29

F. Mehdipour, M. Saheb Zamani, H.R. Ahmady, M. Sedighi, "An Incremental Temporal Partitioning Method for Real-Time Reconfigurable Systems,", Feb 2006.

30

F. Mehdipour, M. Saheb Zamani, M. Sedighi, "Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems,", Aug 2005.

31

M. Najibi Kohneshahri, M. Sedighi, H. Pedram, "Prototyping Globally Asynchronous locally synchronous circuits on commercial synchronous FPGAS,", Feb 2005.

32

F. Mehdipour, M. Saheb Zamani, M. Sedighi, "A New Temporal partition Algorithm and Design flow for Reconfigurable Computing systems,", Nov 2004.

33

F. Mehdipour, M. Saheb Zamani, M. Sedighi, "A New Design flow and Temporal partitioning for Reconfigurable computing systems,", Sep 2004.

34

, M. Sedighi, "Development of a virtual Environment for E-leaming Applications Vsing Virtual Humans,", Dec 2003.

35

M. Rahmani, M. Sedighi, "A new algorithm for resource maneger to enhace the quatliy of service voIP systems,", .

Taught Courses

#

Course title

Description

Headlines

Date

1

Computer Networks Lab

4051

2

Advanced VLSI Design

4051

3

Computer Networks Lab

4051

4

Operating systems Lab

4051

5

Operating systems Lab

4051

6

Operating systems Lab

4051

7

Operating systems Lab

4051

8

Operating systems Lab

4051

9

Computer Architecture Lab

4051

10

Logic Design

4051

11

Advanced Programming Lab.

4051

12

Advanced Programming Lab.

4051

13

Special Topics (Fundamentals if Quantum Computing)

هدف این درس آشنایی دانشجویان رشته کارشناسی مهندسی کامپیوتر، علوم کامپیوتر، و مهندسی برق با اصول و مبانی محاسبات کوانتومی و کاربردهای آن

4042

14

Digital Electronics

4041

15

(Advanced VLSI Circuit Design)

4041

16

(Embedded Systems Modeling and Design)

4032

17

Logic Circuits

4032

Inventions/Patents

#

Invention title

Reg. number

Country

contributers

Reg. date

Exp. date

1

Energy Reduction Method By Approximation For FPGA

2020/06/1

2038/01/19