MORTEZA SAHEB ZAMANI
Professor
Department of Computer Engineering
Computer Networks and Architecture
Department of Computer Engineering
Computer Networks and Architecture
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h-index (Scopus):
15
Citations (Scopus):
763
Supervised PhD Theses
#
Thesis title
By
Date
1
Trade-off energy consumption, accuracy, and latency in Internet of Things-based heart arrhythmia detection systems
Vahid Amini & Morteza Saheb Zamani
June 2024
2
A parallel Computing Architecture for Locating Leaks in water Distribution Networks
Azim Farghadan & Morteza Saheb Zamani
October 2023
3
Hardware Trojan Detection Using Reconfigurability
Reza Fani & Morteza Saheb Zamani
August 2022
Supervised MSc Theses
#
Thesis title
By
Date
1
A parallel Computational Architecture Based on Residual Numbering Systems for Healthcare Applications on FPGA
Sarah Zamani & Morteza Saheb Zamani
August 2024
2
Quantum circuits Synthesis Using Neural Networks
Faezeh Hematzadeh & Morteza Saheb Zamani
August 2024
3
Quantum Circuit Synthesis Considering Interconnections of Qubits
Seyyedmohammadsaeed Fattahi & Morteza Saheb Zamani
September 2023
4
Increase Performance of Incremental Training of Convolutional Neural Networks on FPGA
Farzaneh Arzaghi & Morteza Saheb Zamani
September 2023
5
A High Performance Hardware Accelerator with K-Nearest Neighbor Algorithm for Detecting Leak Location in Water Distribution Networks
Fateme Farajlou & Morteza Saheb Zamani
June 2023
6
A Parallel Computational Architecture for High-Speed Solving of Hydraulic Equations in Cellular Automata
Ali Suvizi & Morteza Saheb Zamani
June 2022
7
Design Space Exploration of Hardware Accelerator for Recurrent Deep Learning on FPGA Devices
Ali Mohammad Pour & Morteza Saheb Zamani
April 2021
8
proposing a reconfigurabchitecture to detect web application attacks
Ali Suzangar & Morteza Saheb Zamani
January 2021
9
A Technique for Partitioning of Circuit in Scalable Quantum Computers
Bahare Jalili & Morteza Saheb Zamani
August 2020
10
Designing an Embedded System for Activity Recognition Using a Surveillance Camera
Sahar Darafsh & Morteza Saheb Zamani
June 2020
11
Hardware Trojan Horse Detection on Commercial Off-The-Shelf Chips
Jamileh Behzadi & Morteza Saheb Zamani
February 2019
12
Proposing a Placement Method to facilitate Hardware Trojan Detection
Milad Sharbati & Morteza Saheb Zamani
June 2018
13
Improving Trustability of RTL IP Cores
Ramin Norouzzadeh & Morteza Saheb Zamani
June 2018
14
Real-time task scheduler on FPGA
Pouya Mahmoody & Morteza Saheb Zamani
February 2018
15
Finding relevant subset of elementary flux modes in metabolic networks
Faridoddin Shafi & Morteza Saheb Zamani
February 2018
16
Hierarchical Decomposition of Metabolic Networks for Calculation of Elementary Flux Modes
Sina Ghadermarzi & Morteza Saheb Zamani
February 2017
17
Detection of functional Hardware Trojan Horse in reconfigurable chips Bitstream
Seyedmohammadmehdi Sharifonasabi & Morteza Saheb Zamani
February 2017
18
fpga-based reconfigurable cpgs for bipedal walking robot
Elham Ebrahimi & Morteza Saheb Zamani
July 2016
19
A Hardware Architecture for Computing Elementary Flux Modes in Metabolic Networks
Seyede Marzieh Hashemipour Nazari & Morteza Saheb Zamani
February 2016
20
Soft IP Protection In FPGA
Mehrnoush Moradi Haghighi & Morteza Saheb Zamani
October 2015
21
Optimizing quantum cost of reversible circuits using garbage bits
Mehrdad Goharibelili & Morteza Saheb Zamani
September 2015
22
Hardware Trojan horses detection using multi VDD design
Farzaneh Bordbar & Morteza Saheb Zamani
October 2014
23
Optimization of Quantum Circuits Using One Way Quantum Computing
Maryam Eslamy & Morteza Saheb Zamani
October 2014
24
a Region-Aware Testing Method for Hardware Trojan Detection
Mohammad Mahdi Fathollahi Nanekaran & Morteza Saheb Zamani
March 2014
25
search based design of a library for one-way quantum computing model
Ehsan Varvaie & Morteza Saheb Zamani
February 2014
26
Hardware Trojan horse Detection by Varying Supply Voltage Levels
Behnam Omidi & Morteza Saheb Zamani
October 2013
27
improving the performance of network on chips by changing the structure of VIPs
Masoud Ganjkhany & Morteza Saheb Zamani
June 2013
28
analyzing the resistance of design for hardware trust techniques against attackers neutralizing efforts
Shirin Alsadet Aalami & Morteza Saheb Zamani
June 2013
29
accelerating network motif finding algorithm using GPU implementation
Ahmadreza Jahani & Morteza Saheb Zamani
February 2013
30
an efficient simulation of one-way Quantum computing
Eesa Nikahd & Morteza Saheb Zamani
October 2012
31
A test approach for detecting malicious hardware
Arash Nejat & Morteza Saheb Zamani
October 2012
32
acceleration of protein tertiary structure comparion algorithm using FPGA
Somayeh Kashi & Morteza Saheb Zamani
July 2012
33
ensuring hardware trust via trustworthy and trojan free intllectual property cores
Salar Sayedebrahimi & Morteza Saheb Zamani
May 2012
34
vpr tool algoritm optimising
Habib Ollah Seifi & Morteza Saheb Zamani
April 2012
35
a system-level architecture for heterogeneous 3D-FPGAs
Sahar Mousavi Khoee & Morteza Saheb Zamani
February 2012
36
proposing a combined physical unclonable function
Mohnoosh Borjian Boroujeni & Morteza Saheb Zamani
February 2012
37
multi-objective synthesis of reversible logic circuits
Mona Arabzadeh & Morteza Saheb Zamani
October 2011
38
FPGA architecture improvment for timing yield enhancemant in presence of process variation
Fatemehsadat Pourhashemi Naeeni & Morteza Saheb Zamani
February 2011
39
temperature-aware routing in 3-D FPGAs
Amin Ezhdehakosh & Morteza Saheb Zamani
February 2011
40
a scheduling algorithm for quantum circuits to reduce execution time
Hamidreza Lotfalizadeh & Morteza Saheb Zamani
February 2011
41
Proposing a New Method for Scheduling Quantum Circuits in ion-trap technology with the aim of reducing the operation Time of the Circuit
Maryam Yazdani & Morteza Saheb Zamani
July 2010
42
3D FPGA Switch box Design for Area Reduction
Seyyed Ahmad Razavi Majomard & Morteza Saheb Zamani
July 2010
43
Process Variation –aware Placement Algorithm for leakage Power Reduction in FPGAs
Behzad Salami & Morteza Saheb Zamani
July 2010
44
place and route in three dimensional fpgas
Seyyed Hassan Moallem Pour & Morteza Saheb Zamani
May 2010
45
Design of a Fault-Tolerant Routing Connection Architecture for SRAM-Based FPGAs
Hassan Ebrahimi & Morteza Saheb Zamani
December 2009
46
statically multiple output custom instruction generation for configurable processors
Mohammad Hassan Kefayati & Morteza Saheb Zamani
July 2009
47
delay variability modeling in FPGA circuits for physical design
Mahdi Nabiyouni & Morteza Saheb Zamani
July 2009
48
a method to reduce congestion during partitioning- based placement
Hossein Shafiei & Morteza Saheb Zamani
May 2009
49
A hardware core for detecting and generating custom instructions and reconfiguring architecture dynamically
Hasan Asgharian & Morteza Saheb Zamani
April 2009
50
Emulation of Quantum circuits with FPGA
Mahdi Aminian & Morteza Saheb Zamani
December 2008
51
A NEW METHODOLOGY TO ESTIMATE AND REDUCE CROSSTALK IN PLACEMENT BASED ON A MULTILEVEL ROUTER
Arash Mahdizadeh & Morteza Saheb Zamani
March 2008
52
A STATISTICAL APPROACH FOR DELAY AND POWER OPTIMIZATION USING AN EVOLUTIONARY ALGORITHM
Minoo Mirsaeedi & Morteza Saheb Zamani
February 2008
53
RETIMING DRIVEN PLACEMENT FOR PERFORMANCE OPTIMIZATION
Adel Dokhanchi & Morteza Saheb Zamani
February 2008
54
A NEW APPROACH TO PARTITIONING FOR REGISTER PLACEMENT TO OPTIMIZE CLOCK NETWORK
Zahra Lak Chalsepari & Morteza Saheb Zamani
August 2007
55
TECHNOLOGY REMAPPING WITH ROUTING CONGESTON REDUCTION CONSIDERATION
Abbas Ali Arabi Mazraeh Shahi & Morteza Saheb Zamani
June 2007
56
AN INTEGRATED APPROACH TO THE PLACEMENT AND ROUTING TO REDUCE TOTAL WIRE LENGTH AND CONGESTION
Mostafa Rezvani & Morteza Saheb Zamani
June 2007
57
NON-TREE CLOCK ROUTING FOR REDUCING DELAY UNCETAINTY
Maryam Taajobian & Morteza Saheb Zamani
April 2007
58
A NEW METHOD FOR BUFFER INSERTION TO REDUCE INTERCONNECT DELAYS IN VLSI CIRCUITS
Hamidreza Kheirabadi & Morteza Saheb Zamani
December 2006
Books
#
Title
Author(s)
Publisher country
publication date
version
Portal Records
1
Computer-Aided Digital Systems Design
Morteza Saheb Zamani
Iran (Islamic Republic of)
June 2019
1
Journal Papers
Portal Records
1
Azim Farghadan, Morteza Saheb Zamani, Mohammadreza Jalili Ghazizadeh, "A fault-injection-based approach to leak localization in water distribution networks using an ensemble model of Bayesian classifiers", JOURNAL OF PROCESS CONTROL, December 2023
Vol. 132,
Num. 103110,
Page 1-15,
December 2023,
2
Ali Suvizi, Azim Farghadan, Morteza Saheb Zamani, "A Parallel Computing Architecture Based on Cellular Automata for Hydraulic Analysis of Water Distrubution Networks", JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, April 2023
Vol. 178,
Num. 0,
Page 11-28,
April 2023,
3
Eesa Nikahd, Morteza Saheb Zamani, Mehdi Sedighi, "Low-overhead code concatenation approaches for universal quantum computation", QUANTUM INFORMATION PROCESSING, January 2023
Vol. 22,
Num. 1,
Page 79-102,
January 2023,
4
Vahid Amini, Mahmoud Momtazpoor, Morteza Saheb Zamani, "An Energy-Efficient and Accuracy-Aware Edge Computing Framework for Heart Arrhythmia Detection: A Joint Model Selection and Task Offloading Approach", JOURNAL OF SUPERCOMPUTING, December 2022
Vol. 1,
Num. 1,
Page 1-1,
December 2022,
5
Azim Farghadan, Morteza Saheb Zamani, Mohammadreza Jalili Ghazizadeh, "Steady-State Hydraulic Analysis Based on Cellular Automata Using a Parallel Paradigm", JOURNAL OF WATER RESOURCES PLANNING AND MANAGEMENT-ASCE, November 2022
Vol. 148,
Num. 11,
Page 1-13,
November 2022,
6
Reza Fani, Morteza Saheb Zamani, "Runtime hardware Trojan detection byreconfigurable monitoring circuits", JOURNAL OF SUPERCOMPUTING, March 2022
Vol. 78,
Num. 7,
Page 12726-12752,
March 2022,
7
Mohammad Hadi Mottaghi Khezri, Mehdi Sedighi, Morteza Saheb Zamani, "FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects", IEEE TRANSACTIONS ON COMPUTERS, November 2021
Vol. 71,
Num. 11,
Page 1-1,
November 2021,
8
Eesa Nikahd, Naser Mohammadzadeh, Mehdi Sedighi, Morteza Saheb Zamani, "Automated window-based partitioning of quantum circuits", PHYSICA SCRIPTA, March 2021
Vol. 96,
Num. 3,
Page 1-19,
March 2021,
9
Mona Arabzadeh, Mehdi Sedighi, Morteza Saheb Zamani, Sayed-Amir Marashi, "A system architecture for parallel analysis of flux-balanced metabolic pathways", COMPUTATIONAL BIOLOGY AND CHEMISTRY, June 2020
Vol. 88,
Num. 107309,
Page 1-15,
June 2020,
10
Ghobad Zarrinchian, Morteza Saheb Zamani, "Combinational Counters: A Low Overhead Approach to Address DPA Attacks", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, May 2020
Vol. 29,
Num. 6,
Page 1-19,
May 2020,
11
Mohammad Hadi Mottaghi Khezri, Mehdi Sedighi, Morteza Saheb Zamani, "Aging Mitigation in FPGAs Considering Delay, Power and Temperature", IEEE TRANSACTIONS ON RELIABILITY, June 2019
Vol. 68,
Num. 2,
Page 0-0,
June 2019,
12
Maryam Eslamy, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, "Optimization of One-Way Quantum Computation Measurement Patterns", INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, November 2018
Vol. 57,
Num. 11,
Page 3296-3317,
November 2018,
13
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Sayed-Amir Marashi, "A graph-based approach to analyze flux-balanced pathways in metabolic networks", BIOSYSTEMS, January 2018
Vol. 165,
Num. 0,
Page 40-51,
January 2018,
14
Eesa Nikahd, Mehdi Sedighi, Morteza Saheb Zamani, "Nonuniform code concatenation for universal fault-tolerant quantum computing", PHYSICAL REVIEW A, September 2017
Vol. 96,
Num. 3,
Page 32337-32342,
September 2017,
15
Mahboobeh Houshmand Kaffashian, Mehdi Sedighi, Morteza Saheb Zamani, Koorosh Marjoei, "Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics", ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, May 2017
Vol. 13,
Num. 4,
Page 0-0,
May 2017,
16
Maryam Eslamy, Morteza Saheb Zamani, Mehdi Sedighi, Mahboubeh Hooshmand Kaffashian, "Optimizing Quantum Circuits Using One-Way Quantum Computation based on pattern Geometry", , February 2017
Vol. 14,
Num. 4,
Page 286-298,
February 2017,
17
Koorosh Marjoei, Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, "Quantum-Logic Synthesis Using Improved Block-Based Approach", Iranian Journal of Electrical and Computer Engineering(IJECE), January 2017
Vol. 14,
Num. 3,
Page 239-248,
January 2017,
18
Ghobad Zarrinchian, Morteza Saheb Zamani, "Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection", IEEE TRANSACTIONS ON COMPUTERS, June 2016
Vol. PP,
Num. 99,
Page 1-14,
June 2016,
19
Mona Arabzadeh, Mahboobeh Houshmand Kaffashian, Mehdi Sedighi, Morteza Saheb Zamani, "Quantum-Logic Synthesis of Hermitian Gates", ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, December 2015
Vol. 12,
Num. 4,
Page 0-0,
December 2015,
20
Mehrshad Khosraviani, Morteza Saheb Zamani, Gholamreza Bidkhori, "FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction", BIOINFORMATICS, November 2015
Vol. 11,
Num. 0,
Page 1-11,
November 2015,
21
Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani, "A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, August 2015
Vol. 24,
Num. 8,
Page 1-15,
August 2015,
22
Eesa Nikahd, Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, "One-Way Quantum Computer Simulation", MICROPROCESSORS AND MICROSYSTEMS, March 2015
Vol. 39,
Num. 3,
Page 210-222,
March 2015,
23
Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani, "Improving hardware Trojan detection by retiming", MICROPROCESSORS AND MICROSYSTEMS, March 2015
Vol. 39,
Num. 3,
Page 145-156,
March 2015,
24
Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, "Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates", ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, December 2014
Vol. 11,
Num. 3,
Page 1-10,
December 2014,
25
Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian, "Automatic translation of quantum circuits to optimized one-way quantum computation patterns", QUANTUM INFORMATION PROCESSING, August 2014
Vol. 13,
Num. 9,
Page 1-20,
August 2014,
26
Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, Monireh Houshmand, "Ga-based approach to find the stabilizers of a given sub-space", GENETIC PROGRAMMING AND EVOLVABLE MACHINES, May 2014
Vol. 1,
Num. 1,
Page 1-1,
May 2014,
27
Arash Nejat, Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani, "A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting", MICROPROCESSORS AND MICROSYSTEMS, January 2014
Vol. -,
Num. 1,
Page 1-21,
January 2014,
28
Naser Mohamadzade, Morteza Saheb Zamani, Mehdi Sedighi, "Quantum Circuit Physical Design Methodology with Emphasis on Physical Synthesis", QUANTUM INFORMATION PROCESSING, November 2013
Vol. ,
Num. 0,
Page 1-21,
November 2013,
29
Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi, "A Quantum Physical Design Flow Using ILP and Graph Drawing", QUANTUM INFORMATION PROCESSING, June 2013
Vol. 12,
Num. 7,
Page 1-28,
June 2013,
30
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, "Depth-optimized reversible circuit synthesis", QUANTUM INFORMATION PROCESSING, September 2012
Vol. 12,
Num. 4,
Page 1677-1699,
September 2012,
31
Naser Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "Gate Location Changing: An Optimization Technique for Quantum Circuits", INTERNATIONAL JOURNAL OF QUANTUM INFORMATION, March 2012
Vol. 10,
Num. 3,
Page 1-20,
March 2012,
32
Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh, "Improved Predictability, Timing Yield and Power Consumption Using Hierarchical Highways-on-Chip Planning Methodology", INTEGRATION-THE VLSI JOURNAL, January 2012
Vol. 44,
Num. 2,
Page 123-135,
January 2012,
33
Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, "Block-Based Quantum-Logic Synthesis", QUANTUM INFORMATION & COMPUTATION, March 2011
Vol. 11,
Num. 0,
Page 262-277,
March 2011,
34
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid Reza Zarandi, "Mitigating Soft Errors in SRAM-Based FPGAs by Decoding Configuration Bits in Switch Boxes", MICROELECTRONICS JOURNAL, January 2011
Vol. 42,
Num. 1,
Page 12-20,
January 2011,
35
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian, "Reversible Circuit Synthesis Using a Cycle-Based Approach", ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, December 2010
Vol. 6,
Num. 4,
Page 0-0,
December 2010,
36
Ali Jahanian, Morteza Saheb Zamani, "Early buffer planning with congestion control using buffer requirement map", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, August 2010
Vol. 19,
Num. 5,
Page 949-973,
August 2010,
37
Naser Mohamadzade, Morteza Saheb Zamani, Mehdi Sedighi, "Auxiliary Qubit Selection: A Physical Synthesis Technique for Quantum Circuits", QUANTUM INFORMATION PROCESSING, June 2010
Vol. 9,
Num. 6,
Page 1-16,
June 2010,
38
Ali Jahanian, Morteza Saheb Zamani, "Higher Routability and Reduced Crosstalk Noise by Asynchronous Multiplexing of On-chip Interconnects", SCIENTIA IRANICA TRANSACTION D-COMPUTER SCIENCE & ENGINEERING AND ELECTRICAL ENGINEERING, June 2010
Vol. 17,
Num. 1,
Page 11-24,
June 2010,
39
Naser Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "Quantum Physical Synthesis:Improving Physical Design by Netlist Modifications", Microelectronics Journal, March 2010
Vol. 41,
Num. 4,
Page 0-0,
March 2010,
40
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Synthesis", , December 2009
Vol. ,
Num. 0,
Page 0-0,
December 2009,
41
Mehdi Saeedi, Naser Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Systhesis", , February 2009
Vol. ,
Num. 2,
Page 0-0,
February 2009,
42
Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghiyan, Farhad Mehdipour, "A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms", The CSI Journal on Computer Science and Engineering(JCSE), February 2009
Vol. 5,
Num. 2,
Page 9-15,
February 2009,
43
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, "Synthesis of Reversible Circuits Using A Moving Forward Strategy", , August 2008
Vol. ,
Num. 17,
Page 0-0,
August 2008,
44
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, "An Architecture Framework for an Adaptive Extensible Processor", , August 2008
Vol. ,
Num. 45,
Page 0-0,
August 2008,
45
, Mehdi Saeedi, Morteza Saheb Zamani, "A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems", , June 2008
Vol. ,
Num. 32,
Page 0-0,
June 2008,
46
Ali Jahanian, Morteza Saheb Zamani, "Using metro-on-chip in physical design flow for congestion and routability improvement", , February 2008
Vol. ,
Num. 39,
Page 0-0,
February 2008,
47
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, "improving Performance and Energy Saving in a Reconfigurable Processor Via Accelerating Control Data Flow Graphs", , December 2007
Vol. ,
Num. 12,
Page 0-0,
December 2007,
48
Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, "Evaluation Prediction and Reduction of Routing Congestion", , August 2007
Vol. ,
Num. 38,
Page 0-0,
August 2007,
49
Ali Jahanian, Morteza Saheb Zamani, "Metro-on-Chip:an Effecient Physical Design Technique for Congestion Reduction", , August 2007
Vol. ,
Num. 25,
Page 0-0,
August 2007,
50
Farhad Mehdipour, Morteza Saheb Zamani, Hamidreza Ahmadifar, T. Murakami, "An Integrated Temporal Partitioning and Physical Design Framework for Real-Time Reconfigurable Systems", , February 2006
Vol. ,
Num. 5,
Page 0-0,
February 2006,
51
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, "An Integrated Temporal Partitioning and Physical Design Framework for Static Compilation of Reconfigurable Computing Systems", , January 2006
Vol. ,
Num. 30,
Page 0-0,
January 2006,
52
Morteza Saheb Zamani, "A specification-driven framework for the floorplanning and placement of hierarchical VLSI designs", , September 2004
Vol. ,
Num. 2,
Page 0-0,
September 2004,
Conference Papers
Portal Records
1
Misha Sadeghi, Seyyed Ahmad Razavi Majomard, Morteza Saheb Zamani, "Reducing Reconfiguration Time in FPGAs ", 27th Iranian Conference on Electrical Engineering (ICEE2019), April 2019
2
Milad Sharbati, Ghobad Zarrinchian, Morteza Saheb Zamani, "A Placement Method for Facilitating Detection of Hardware Trojan Horses ", Computer Society of Iran Computer Conference, March 2019
3
Soudabe Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "An efficient and exact synthesis of n-qubit diagonal ring gates into Clifford and T gates ", 26th Iranian Conference on Electrical Engineering, May 2018
4
Elham Ebrahimi, Saeed Shiry Ghidary, Morteza Saheb Zamani, "Fast FPGA-Based Method for Matsuoka Parameters Tuning ", International Conference on Signal Processing and Intelligent (ICSPIS), December 2016
5
Eesa Nikahd, Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, "GOWQS: Graph-Based One-Way Quantum Computation Simulator ", Iranian Conference on Electrical Engineering, May 2016
6
Maryam Eslamy, Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, "Geometry-Based Signal Shifting of One-Way Quantum Computation Measurement
Patterns ", Iranian Conference on Electrical Engineering, May 2016
7
Mehrnoush Moradi Haghighi, Morteza Saheb Zamani, "Soft IP Protection: An Active Approach Based on Hardware Authentication ", Iranian Conference on Electrical Engineering, May 2016
8
Faranak Adinehzadeh, Naser Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "Proposing an Approach for Scheduling and Routing of Quantum Circuits with Toffoli Gates in Ion-Trap Technology ", 22nd Iranian Conference on Electrical Engineering, May 2014
9
Mina Chookhachi Zadeh Moghadam, Naser Mohamadzade, Mehdi Sedighi, Morteza Saheb Zamani, "A Hierarchical Layout Generation Method for Quantum Circuits ", International Symposium on Computer Architecture and Digital Systems (CADS’13), October 2013
10
Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani, Shirin Alsadet Aalami, "Neutralizing a Design for Hardware Trust Technique ", International Symposium on Computer Architecture and Digital Systems (CADS’13), October 2013
11
Zahra Nabizadeh.Shahrebabak, Mehdi Sedighi, Morteza Saheb Zamani, "Simultaneous Improvement of Area, Delay, and Fault Tolerance in Quantum Circuits ", International Symposium on Computer Architecture and Digital Systems (CADS’13), October 2013
12
Seyyed Ahmad Razavi Majomard, Morteza Saheb Zamani, "Improving Bitstream Compression by Modifying FPGA Architecture ", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’13), February 2013
13
Eesa Nikahd, Mahboobeh Houshmand Kaffashian, Morteza Saheb Zamani, Mehdi Sedighi, "OWQS: One-Way Quantum Computation Simulator ", IEEE Euromicro Conference on Digital System Design (DSD’12), September 2012
14
Somayeh Kashi, Morteza Saheb Zamani, "Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins ", IEEE Euromicro Conference on Digital System Design (DSD’12), September 2012
15
Mahboobeh Houshmand Kaffashian, Mohammad Hossein Samavatian, Morteza Saheb Zamani, Mehdi Sedighi, "Extracting One-way Quantum Computation Patterns from Quantum Circuits ", International Symposium on Computer Architecture and Digital Systems (CADS’12), May 2012
16
Fatemehsadat Pourhashemi Naeeni, Morteza Saheb Zamani, "Timing Yield Improvement of FPGAs Utilizing Enhanced Architectures and Multiple Configurations Under Process Variation ", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’12), February 2012
17
Seyyed Hassan Moallem Pour, Seyyed Ahmad Razavi Majomard, Morteza Saheb Zamani, "TSV Reduction in Homogeneous 3D FPGAs by Logic Resource and Input Pad Replication ", IEEE International 3D System
Integration Conference 2012 (3DIC’12), January 2012
18
Behzad Salami, Morteza Saheb Zamani, Ali Jahanian, "VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs ", EEE Euromicro Conference on Digital System Design (DSD’11), September 2011
19
Behzad Salami, Morteza Saheb Zamani, "A Prediction Model For Estimating Leakage Power Consumption of Routing Resources in FPGAs ", Asia Symposium on Quality Electronic Design (ASQED’11), July 2011
20
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, "Logical-Depth-Oriented Reversible Logic Synthesis ", International Workshop on Logic Synthesis (IWLS’11), June 2011
21
Fatemehsadat Pourhashemi Naeeni, Morteza Saheb Zamani, "Evaluation of FPGA Routing Architectures Under Process Variation ", ACM Great Lakes Symposium on VLSI (GLSVLSI’11), May 2011
22
Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi Majomard, "A Switch Box Architecture to Mitigate Bridging Faults in SRAM-Based FPGAs ", IEEE International Symposium on Defect and Fault Tolerance (DFT10), October 2010
23
Ali Jahanian, Morteza Saheb Zamani, "Chip Master Planning: An Efficient Methodology to
Improve Design Closure and Complexity
Management of Ultra Large Chips ", CSI International Symposium on Computer Architecture and Digital Systems, September 2010
24
Delasa Aghamirzaie, Seyyed Ahmad Razavi Majomard, Morteza Saheb Zamani, Mahdi Nabiyouni, "Reduction of Process Variation Effect on FPGAs Using Multiple Configurations ", IEEE/IFIP International Conference on Very Large-Scale Integration (VLSI-SOC’10), September 2010
25
Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani, "Rule-Based Optimization of Reversible Circuits ", Asia and South Pacific Design Automation Conference, January 2010
26
Hassan Ebrahimi, Morteza Saheb Zamani, Hamid Reza Zarandi, "A Decoder-Based Switch Box to Mitigate Soft Errors in SRAM-Based FPGAs ", IEEE Asia and South-Pacific Design Automation Conference, January 2010
27
Seyyed Ahmad Razavi Majomard, Morteza Saheb Zamani, "A tileable switch module architecture for honogenous 3D FPGAs ", , September 2009
28
[en-name N/A], Morteza Saheb Zamani, Mehdi Sedighi, "Improving latency of quantum circuits by gate exchanging ", , August 2009
29
Mehdi Saeedi, Morteza Saheb Zamani, "A Library-Based Synthesis Approach for Reversible Logic ", International Workshop on Logic & Synthesis, August 2009
30
Ali Jahanian, Morteza Saheb Zamani, "Improved Performance and Yield with Chip Master Planning Design Methodology ", ACM Great Lakes Symposium on VLSI, May 2009
31
Naser Mohamadzade, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani, "Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network ", Design, Automation & Test in Europe Conference, April 2009
32
Zahra Sasanian, Mehdi Sedighi, Morteza Saheb Zamani, "A Cycle Based Synthesis Algorithm for Reversible logic ", , January 2009
33
Mehdi Saeedi, [en-name N/A], Mehdi Sedighi, Morteza Saheb Zamani, "Performance and timing yield enhancement using highway on chip planning ", , September 2008
34
Morteza Saheb Zamani, Maryam Taajobian, Mehdi Sedighi, "An efficient non tree clock routing algorithm for reducing delay uncertainty ", , September 2008
35
Ehsan Khish Ardestani Zadeh, Morteza Saheb Zamani, Mehdi Sedighi, "A fast transormation based synthesis algorithm for reversible circuits ", , September 2008
36
Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Sedighi, "Multi objective statistical yield enhancement using evolutionary algorithm ", , September 2008
37
Ali Jahanian, Morteza Saheb Zamani, "Evaluation and improvement of quantum synthesis algorithms based on a thorough set of metrics ", , September 2008
38
Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani, "Performance improvement of physical retiming with shortcut insertion ", , April 2008
39
Mehdi Saeedi, Morteza Saheb Zamani, "Shared PPRM a Memory efficient representation for boolean reversible functions ", , April 2008
40
Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi, "Simultanous Gate Siting and Skew Scheduling to Statistical Yield Improvement ", , April 2008
41
[en-name N/A], Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, "FPGA based circuit model emulation of quantum algorithms ", , April 2008
42
Arash Mahdizadeh, Morteza Saheb Zamani, Hassan Shafie, "An Efficient Method of Estimate Crosstalk After Placement Incorporating a Reduction Scheme ", , April 2008
43
Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi Kohneshahri, "Evaluation the metro on chip methodology to improve the congestion and routability ", , March 2008
44
Arash Mahdizadeh, Morteza Saheb Zamani, "Proposing an efficient method to estimate crosstalk after placement in VLSI circuits ", , March 2008
45
Arash Mahdizadeh, Morteza Saheb Zamani, "Proposing an efficient method to estimate crosstalk after plasement in VLSI circuits ", , March 2008
46
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, "Design space exploration for a coarse grain accelerator ", , January 2008
47
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, "Moving forward: a non search based synthesis method toward efficient CNOT based quantum circuit synthesis algorithm ", , January 2008
48
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, "A novel synthesis algorithm for reversible circuits ", , November 2007
49
Arash Mahdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, "An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor ", , October 2007
50
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sadeghi, "A forward looking non search based synthesis algorithm for reversible circuits ", , September 2007
51
Minoo Mirsaeedi, Morteza Saheb Zamani, "An evolutionary approach to statistical design space exploration ", , September 2007
52
Ali Jahanian, Morteza Saheb Zamani, Mehrdad Najibi Kohneshahri, "Using asynchronous serial transmission in physical design for congestion reduction ", , September 2007
53
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, "Algebraic characterization of CNOT- based quantum circuits with its applications on logic synthesis ", , August 2007
54
Arash Mahdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Farhad Mehdipour, "Performance Enhancement of an Adaptive Dynamic Extensible Processor by Using a Heterogeneous Reconfigurable Functional Unit ", , July 2007
55
Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, "On the behavior of substitution based reversible circuit synthesis algorithms: investigation and improvement ", , May 2007
56
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani, "A new methodology for quantum circuit synthesis CNOT based circuits as an example ", , May 2007
57
Hamidreza Kheyrabadi, Morteza Saheb Zamani, Mahdi Saeidi, "An efficient analytical approach to path based buffer insertion ", , May 2007
58
Ali Jahanian, Morteza Saheb Zamani, "Improved Timing Closure by Early Buffer Planning in Floor-Placement Design Flow ", , March 2007
59
Hamidreza Kheyrabadi, Morteza Saheb Zamani, "An efficient net ordering algorithm for buffer insertion ", , March 2007
60
Mahdi Saeidi, Morteza Saheb Zamani, Saadat Pourmozafari, "The effects of process variation on noise avoidance technique in VLSI circuits ", , February 2007
61
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, "A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor ", , August 2006
62
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Hamid Noori, "GifT A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs ", , June 2006
63
Morteza Saheb Zamani, Mehdi Saeedi, Ali Jahanian, "Prediction and reduction of routing congestion ", , April 2006
64
Farhad Mehdipour, Morteza Saheb Zamani, "Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework ", , April 2006
65
Ali Jahanian, Morteza Saheb Zamani, "Multi-Level Buffer Block Planning and Buffer Insertion for Large Circuits ", , March 2006
66
Farhad Mehdipour, Morteza Saheb Zamani, Hamid Reza Ahmady, Mehdi Sedighi, "An Incremental Temporal Partitioning Method for Real-Time Reconfigurable Systems ", , February 2006
67
Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, "Congestion prediction: from metrics definition to routing estimation ", , December 2005
68
Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghiyan, Farhad Mehdipour, "A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms ", , December 2005
69
Morteza Saheb Zamani, Masoud Sabaei, "a novel reconfigurable hardware architecture for IP address lookup ", , October 2005
70
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, "Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems ", , August 2005
71
Arash Hariri, Reza Rastegar, [en-name N/A], Morteza Saheb Zamani, Mohammad Reza Meybodi, "Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution ", , June 2005
72
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi, "Parallel Hardware Implementation of Cellular Learning Automata based Evolutionary Computing on FPGA ", , April 2005
73
Morteza Saheb Zamani, Mahdi Saeidi, "an efficient congestion reduction algorithm based on contour plotthng ", , March 2005
74
Morteza Saheb Zamani, "parallel hardware implementation of automata based evolutionary computting FPGA ", , March 2005
75
Morteza Saheb Zamani, "a true congestion prediction method based on routers intelligence ", , March 2005
76
Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghiyan, Farhad Mehdipour, "A High performance Reconfigurable Implementation of DES- Like Algorithms ", , December 2004
77
Bahram Najafi Uchevler, Babak Sadeghiyan, Morteza Saheb Zamani, Ali Valizadeh, "High speed Implementation of serpent Algorithm ", , December 2004
78
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, "A New Temporal partition Algorithm and Design flow for Reconfigurable Computing systems ", , November 2004
79
Babak Sadeghiyan, Morteza Saheb Zamani, Bahram Najafi Uchevler, "Reconfiguration of RTL Designs Using JBits ", , September 2004
80
Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghiyan, "Hardware Implementation of LOKI Block cipher ", , September 2004
81
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, "A New Design flow and Temporal partitioning for Reconfigurable computing systems ", , September 2004
82
Morteza Saheb Zamani, Saeed Kazemi, "Hierarchical global routing integrated with floorplanning and placement ", , February 2004
83
Mostafa Ersali Salehi Nasab, Hossein Pedram, Morteza Saheb Zamani, "A Transistor-Level Placement Tool for Asynchronous Circuits ", , February 2004
84
Morteza Saheb Zamani, Masoud Soleimani, "Rectilinear floorplanning of FPGAs using kohonen map ", , July 2003
85
Morteza Saheb Zamani, Farhad Mehdipour, Mohammad Reza Meybodi, "Image Restoration Using Cellular Learning Automata Implemented on FPGA ", , May 2003
86
Morteza Saheb Zamani, Farhad Mehdipour, Mohammad Reza Meybodi, "Implementation of cellular learning automata on reconfigurable systems ", , May 2003
87
Morteza Saheb Zamani, Ehsan Esmaili Moshgenani, "Reducing power consumption in FPGA routing ", , May 2003
88
Morteza Saheb Zamani, Mehran Mahramian Moallem, Hassan Taheri, [en-name N/A], "Steiner minimum tree with two-dimensional self-assembly DNA ", , April 2003
89
Morteza Saheb Zamani, Mehran Mahramian Moallem, Hassan Taheri, [en-name N/A], "Steriner Minimum tree for VLSI global routing using DNA computing ", , February 2003
90
Morteza Saheb Zamani, Mehran Mahramian Moallem, Hassan Taheri, [en-name N/A], "Steiner Minimum Tree and its application in global routing using DNA computing ", , September 2002
91
Morteza Saheb Zamani, Farhad Mehdipour, "An efficient method for placement of VLSI designs with kohonen map ", , June 1999
92
Morteza Saheb Zamani, Masoud Soleimani, "Rectilinear floorplanning of FPGAs using Kohonen map ", , June 1999
93
Morteza Saheb Zamani, Farhad Mehdipour, "using kohonen maps for the placement of regular VLSI designs ", , January 1999
94
Morteza Saheb Zamani, G.R. Hellestrand, "Placement with self-organizing neural networks ", , November 1995
95
Morteza Saheb Zamani, G.R. Hellestrand, "A neural network approach to the placement problem ", , August 1995
96
Morteza Saheb Zamani, G.R. Hellestrand, "The floorplanning of hierachical designs using self-organizing neural networks ", , August 1995
97
Morteza Saheb Zamani, G.R. Hellestrand, "A neural network approach to the floorplanning of hierachical VLSI designs ", , May 1995
98
Morteza Saheb Zamani, G.R. Hellestrand, "A stepwise refinement algorithm for integrated floorplanning, placement and routing of hierarchical designs ", , April 1995
Taught Courses
#
Course title
Description
Headlines
Date
1
Logic Circuits
To gain knowledge and skill to design, analyze and debug digital circuits
Fall 2024
2
(Reconfigurable Systems)
Introduction to reconfigurable systems and device and research topics in this field
Fall 2024
3
Logic Circuits
To gain knowledge and skill to design, analyze and debug digital circuits
Spring 2024
4
Programmable Digital Systems Design
Modern methods for digital system design and verification
Spring 2024
5
Logic Circuits
To gain knowledge and skill to design, analyze and debug digital circuits
Fall 2023
6
(Reconfigurable Systems)
Introduction to reconfigurable systems and device and research topics in this field
Fall 2023
7
(VLSI Design Algorithms)
Introducing VLSI physical design problems and algorithms for chip planning, placement and routing
Spring 2023
8
Logic Circuits
To gain knowledge and skill to design, analyze and debug digital circuits
Spring 2023