MORTEZA SAHEB ZAMANI - Amirkabir University of Technology

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Amirkabir University of Technology

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MORTEZA SAHEB ZAMANI

Professor
Department of Computer Engineering
Computer Networks and Architecture

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Email:

szamani

aut.ac.ir

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h-index (Scopus):

15.00

Citations (Scopus):

763

Supervised PhD Theses

Thesis title

Date

Trade-off energy consumption, accuracy, and latency in Internet of Things-based heart arrhythmia detection systems

VAHID AMINI
Other Supervisor: Mahmoud Momtazpoor

2024 Jun

A parallel Computing Architecture for Locating Leaks in water Distribution Networks

AZIM FARGHADAN

2023 Oct

Hardware Trojan Detection Using Reconfigurability

REZA FANI

2022 Aug

Supervised MSc Theses

Thesis title

Date

Convolutional Neural Network Acceleration Based on Residue Number System on FPGA

SARAH ZAMANI

2024 Aug

Quantum Circuit Synthesis Using Reinforcement Learning Based on MCTS

FAEZEH HEMATZADEH
Other Supervisor: MEHDI SEDIGHI

2024 Aug

Quantum Circuit Synthesis Considering Interconnections of Qubits

SEYYEDMOHAMMADSAEED FATTAHI & MEHDI SEDIGHI
Other Supervisor:

2023 Sep

Increase Performance of Incremental Training of Convolutional Neural Networks on FPGA

FARZANEH ARZAGHI

2023 Sep

A High Performance Hardware Accelerator with K-Nearest Neighbor Algorithm for Detecting Leak Location in Water Distribution Networks

FATEMEH FARAJLOU

2023 Jun

A Parallel Computational Architecture for High-Speed Solving of Hydraulic Equations in Cellular Automata

ALI SUVIZI

2022 Jun

Design Space Exploration of Hardware Accelerator for Recurrent Deep Learning on FPGA Devices

ALI MOHAMMAD POUR

2021 Apr

proposing a reconfigurabchitecture to detect web application attacks

ALI SUZANGAR

2021 Jan

A Technique for Partitioning of Circuit in Scalable Quantum Computers

BAHARE JALILI
Other Supervisor: MEHDI SEDIGHI

2020 Aug

Designing an Embedded System for Activity Recognition Using a Surveillance Camera

SAHAR DARAFSH & SAEED SHIRY GHIDARY
Other Supervisor:

2020 Jun

Hardware Trojan Horse Detection on Commercial Off-The-Shelf Chips

JAMILEH BEHZADI

2019 Feb

Proposing a Placement Method to facilitate Hardware Trojan Detection

MILAD SHARBATI

2018 Jun

Improving Trustability of RTL IP Cores

RAMIN NOROUZZADEH

2018 Jun

Real-time task scheduler on FPGA

POUYA MAHMOODY

2018 Feb

Finding relevant subset of elementary flux modes in metabolic networks

FARIDODDIN SHAFI

2018 Feb

Hierarchical Decomposition of Metabolic Networks for Calculation of Elementary Flux Modes

SINA GHADERMARZI

2017 Feb

Detection of functional Hardware Trojan Horse in reconfigurable chips Bitstream

SEYEDMOHAMMADMEHDI SHARIFONASABI

2017 Feb

fpga-based reconfigurable cpgs for bipedal walking robot

ELHAM EBRAHIMI & SAEED SHIRY GHIDARY
Other Supervisor:

2016 Jul

A Hardware Architecture for Computing Elementary Flux Modes in Metabolic Networks

SEYEDE MARZIEH HASHEMIPOUR NAZARI

2016 Feb

Soft IP Protection In FPGA

MEHRNOUSH MORADI HAGHIGHI

2015 Oct

Optimizing quantum cost of reversible circuits using garbage bits

MEHRDAD GOHARIBELILI

2015 Sep

Optimization of Quantum Circuits Using One Way Quantum Computing

MARYAM ESLAMY

2014 Oct

Hardware Trojan horses detection using multi VDD design

FARZANEH BORDBAR

2014 Oct

a Region-Aware Testing Method for Hardware Trojan Detection

MOHAMMAD MAHDI FATHOLLAHI NANEKARAN

2014 Mar

search based design of a library for one-way quantum computing model

EHSAN VARVAIE

2014 Feb

Hardware Trojan horse Detection by Varying Supply Voltage Levels

BEHNAM OMIDI

2013 Oct

analyzing the resistance of design for hardware trust techniques against attackers neutralizing efforts

SHIRIN ALSADET AALAMI

2013 Jun

improving the performance of network on chips by changing the structure of VIPs

MASOUD GANJKHANY

2013 Jun

accelerating network motif finding algorithm using GPU implementation

AHMADREZA JAHANI

2013 Feb

an efficient simulation of one-way Quantum computing

EESA NIKAHD

2012 Oct

A test approach for detecting malicious hardware

ARASH NEJAT

2012 Oct

acceleration of protein tertiary structure comparion algorithm using FPGA

SOMAYEH KASHI

2012 Jul

ensuring hardware trust via trustworthy and trojan free intllectual property cores

SALAR SAYEDEBRAHIMI

2012 May

vpr tool algoritm optimising

HABIB OLLAH SEIFI

2012 Apr

proposing a combined physical unclonable function

MOHNOOSH BORJIAN BOROUJENI

2012 Feb

a system-level architecture for heterogeneous 3D-FPGAs

SAHAR MOUSAVI KHOEE

2012 Feb

multi-objective synthesis of reversible logic circuits

MONA ARABZADEH

2011 Oct

a scheduling algorithm for quantum circuits to reduce execution time

HAMIDREZA LOTFALIZADEH

2011 Feb

FPGA architecture improvment for timing yield enhancemant in presence of process variation

FATEMEHSADAT POURHASHEMI NAEENI

2011 Feb

temperature-aware routing in 3-D FPGAs

AMIN EZHDEHAKOSH

2011 Feb

Proposing a New Method for Scheduling Quantum Circuits in ion-trap technology with the aim of reducing the operation Time of the Circuit

MARYAM YAZDANI

2010 Jul

3D FPGA Switch box Design for Area Reduction

SEYYED AHMAD RAZAVI MAJOMARD

2010 Jul

Process Variation -aware Placement Algorithm for leakage Power Reduction in FPGAs

BEHZAD SALAMI

2010 Jul

place and route in three dimensional fpgas

SEYYED HASSAN MOALLEM POUR

2010 May

Design of a Fault-Tolerant Routing Connection Architecture for SRAM-Based FPGAs

HASSAN EBRAHIMI

2009 Dec

delay variability modeling in FPGA circuits for physical design

MAHDI NABIYOUNI

2009 Jul

statically multiple output custom instruction generation for configurable processors

MOHAMMAD HASSAN KEFAYATI

2009 Jul

a method to reduce congestion during partitioning- based placement

HOSSEIN SHAFIEI

2009 May

Statistical Static Timing Analysis in Global Placement Considering Cell Location Variability

SARA SHAFEE

2009 May

A hardware core for detecting and generating custom instructions and reconfiguring architecture dynamically

HASAN ASGHARIAN

2009 Apr

Emulation of Quantum circuits with FPGA

MAHDI AMINIAN

2008 Dec

Global Routing in X-Architecture Through Dense Region Expansion

SOLMAZ DARVISH

2008 Apr

A NEW METHODOLOGY TO ESTIMATE AND REDUCE CROSSTALK IN PLACEMENT BASED ON A MULTILEVEL ROUTER

ARASH MAHDIZADEH

2008 Mar

RETIMING DRIVEN PLACEMENT FOR PERFORMANCE OPTIMIZATION

ADEL DOKHANCHI

2008 Feb

A STATISTICAL APPROACH FOR DELAY AND POWER OPTIMIZATION USING AN EVOLUTIONARY ALGORITHM

MINOO MIRSAEEDI

2008 Feb

Steiner Tree Construction in X-Architecture in the Presence of Obstacles

FARNAZ MOHAMMADIYEH FAMILY

2007 Oct

A NEW APPROACH TO PARTITIONING FOR REGISTER PLACEMENT TO OPTIMIZE CLOCK NETWORK

ZAHRA LAK CHALSEPARI

2007 Aug

AN INTEGRATED APPROACH TO THE PLACEMENT AND ROUTING TO REDUCE TOTAL WIRE LENGTH AND CONGESTION

MOSTAFA REZVANI

2007 Jun

TECHNOLOGY REMAPPING WITH ROUTING CONGESTON REDUCTION CONSIDERATION

ABBAS ALI ARABI MAZRAEH SHAHI

2007 Jun

NON-TREE CLOCK ROUTING FOR REDUCING DELAY UNCETAINTY

MARYAM TAAJOBIAN

2007 Apr

A NEW METHOD FOR BUFFER INSERTION TO REDUCE INTERCONNECT DELAYS IN VLSI CIRCUITS

HAMIDREZA KHEIRABADI

2006 Dec

FPGA-Based Hardware Acceleration of Remaining Useful Life Prediction of Rotating Machinery Using Transformer Neural Network

REZA ADINEPOUR

2026 Jun

Quantum Circuit Partitiong Quality Prediction for Implementation on Distributed Quantum Computers

MOHAMMAD RAMEZANI
Other Supervisor: MEHDI SEDIGHI

2025 Sep

Acceleration of GAN Networks Using FPGA

MOHAMMAD MIRZAEI

2025 Mar

Books

Title

Author(s)

Publisher country

publication date

version

Computer-Aided Digital Systems Design

M. Saheb Zamani

Iran

Journal Papers

A. Farghadan, M. Saheb Zamani, Mohammadreza Jalili Ghazizadeh, "A fault-injection-based approach to leak localization in water distribution networks using an ensemble model of Bayesian classifiers", Journal of Process Control, 2023 Dec vol. 132, no. 103110, pp.1-15, 2023.

A. Suvizi, A. Farghadan, M. Saheb Zamani, "A Parallel Computing Architecture Based on Cellular Automata for Hydraulic Analysis of Water Distrubution Networks", Journal of Parallel and Distributed Computing, 2023 Apr vol. 178, no. 0, pp.11-28, 2023.

Eesa Nikahd, M. Saheb Zamani, M. Sedighi, "Low-overhead code concatenation approaches for universal quantum computation", Quantum Information Processing, 2023 Jan vol. 22, no. 1, pp.79-102, 2023.

V. Amini, M. Momtazpoor, M. Saheb Zamani, "An Energy-Efficient and Accuracy-Aware Edge Computing Framework for Heart Arrhythmia Detection: A Joint Model Selection and Task Offloading Approach", Journal of Supercomputing, 2022 Dec vol. 1, no. 1, pp.1-1, 2022.

A. Farghadan, M. Saheb Zamani, Mohammadreza Jalili Ghazizadeh, "Steady-State Hydraulic Analysis Based on Cellular Automata Using a Parallel Paradigm", Journal of Water Resources Planning and Management-Asce, 2022 Nov vol. 148, no. 11, pp.1-13, 2022.

R. Fani, M. Saheb Zamani, "Runtime hardware Trojan detection byreconfigurable monitoring circuits", Journal of Supercomputing, 2022 Mar vol. 78, no. 7, pp.12726-12752, 2022.

M.H. Mottaghi Khezri, M. Sedighi, M. Saheb Zamani, "FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects", Ieee Transactions On Computers, 2021 Nov vol. 71, no. 11, pp.1-1, 2021.

E. Nikahd, Naser Mohammadzadeh, M. Sedighi, M. Saheb Zamani, "Automated window-based partitioning of quantum circuits", Physica Scripta, 2021 Mar vol. 96, no. 3, pp.1-19, 2021.

M. Arabzadeh, M. Sedighi, M. Saheb Zamani, Sayed-amir Marashi, "A system architecture for parallel analysis of flux-balanced metabolic pathways", Computational Biology and Chemistry, 2020 Jun vol. 88, no. 107309, pp.1-15, 2020.

G. Zarrinchian, M. Saheb Zamani, "Combinational Counters: A Low Overhead Approach to Address DPA Attacks", Journal of Circuits Systems and Computers, 2020 May vol. 29, no. 6, pp.1-19, 2020.

M.H. Mottaghi Khezri, M. Sedighi, M. Saheb Zamani, "Aging Mitigation in FPGAs Considering Delay, Power and Temperature", Ieee Transactions On Reliability, 2019 Jun vol. 68, no. 2, , 2019.

M. Eslamy, Mahboobeh Houshmand, M. Saheb Zamani, M. Sedighi, "Optimization of One-Way Quantum Computation Measurement Patterns", International Journal of Theoretical Physics, 2018 Nov vol. 57, no. 11, pp.3296-3317, 2018.

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, Sayed-amir Marashi, "A graph-based approach to analyze flux-balanced pathways in metabolic networks", Biosystems, 2018 Jan vol. 165, no. 0, pp.40-51, 2018.

E. Nikahd, M. Sedighi, M. Saheb Zamani, "Nonuniform code concatenation for universal fault-tolerant quantum computing", Physical Review A, 2017 Sep vol. 96, no. 3, pp.32337-32342, 2017.

M. Houshmand Kaffashian, M. Sedighi, M. Saheb Zamani, K. Marjoei, "Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics", Acm Journal On Emerging Technologies In Computing Systems, 2017 May vol. 13, no. 4, , 2017.

M. Eslamy, M. Saheb Zamani, M. Sedighi, Mahboubeh Hooshmand Kaffashian, "Optimizing Quantum Circuits Using One-Way Quantum Computation based on pattern Geometry", , 2017 Feb vol. 14, no. 4, pp.286-298, 2017.

K. Marjoei, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "Quantum-Logic Synthesis Using Improved Block-Based Approach", Iranian Journal of Electrical and Computer Engineering, 2017 Jan vol. 14, no. 3, pp.239-248, 2017.

G. Zarrinchian, M. Saheb Zamani, "Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection", Ieee Transactions On Computers, 2016 Jun vol. PP, no. 99, pp.1-14, 2016.

M. Arabzadeh, M. Houshmand Kaffashian, M. Sedighi, M. Saheb Zamani, "Quantum-Logic Synthesis of Hermitian Gates", Acm Journal On Emerging Technologies In Computing Systems, 2015 Dec vol. 12, no. 4, , 2015.

M. Khosraviani, M. Saheb Zamani, Gholamreza Bidkhori, "FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction", Bioinformatics, 2015 Nov vol. 11, no. 0, pp.1-11, 2015.

S.M.H. Shekarian, M. Saheb Zamani, "A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust", Journal of Circuits Systems and Computers, 2015 Aug vol. 24, no. 8, pp.1-15, 2015.

S.M.H. Shekarian, M. Saheb Zamani, "Improving hardware Trojan detection by retiming", Microprocessors and Microsystems, 2015 Mar vol. 39, no. 3, pp.145-156, 2015.

E. Nikahd, M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, "One-Way Quantum Computer Simulation", Microprocessors and Microsystems, 2015 Mar vol. 39, no. 3, pp.210-222, 2015.

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, M. Arabzadeh, "Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates", Acm Journal On Emerging Technologies In Computing Systems, 2014 Dec vol. 11, no. 3, pp.1-10, 2014.

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, M.H. Samavatian, "Automatic translation of quantum circuits to optimized one-way quantum computation patterns", Quantum Information Processing, 2014 Aug vol. 13, no. 9, pp.1-20, 2014.

M. Houshmand Kaffashian, M. Saheb Zamani, M. Sedighi, Monireh Houshmand, "Ga-based approach to find the stabilizers of a given sub-space", Genetic Programming and Evolvable Machines, 2014 May vol. 1, no. 1, pp.1-1, 2014.

A. Nejat, S.M.H. Shekarian, M. Saheb Zamani, "A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting", Microprocessors and Microsystems, 2014 Jan vol. -, no. 1, pp.1-21, 2014.

N. Mohamadzade, M. Saheb Zamani, M. Sedighi, "Quantum Circuit Physical Design Methodology with Emphasis on Physical Synthesis", Quantum Information Processing, 2013 Nov vol. , no. 0, pp.1-21, 2013.

M. Yazdani, M. Saheb Zamani, M. Sedighi, "A Quantum Physical Design Flow Using ILP and Graph Drawing", Quantum Information Processing, 2013 Jun vol. 12, no. 7, pp.1-28, 2013.

M. Arabzadeh, M. Saheb Zamani, M. Sedighi, M. Saeedi, "Depth-optimized reversible circuit synthesis", Quantum Information Processing, 2012 Sep vol. 12, no. 4, pp.1677-1699, 2012.

N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Gate Location Changing: An Optimization Technique for Quantum Circuits", International Journal of Quantum Information, 2012 Mar vol. 10, no. 3, pp.1-20, 2012.

A. Jahanian, M. Saheb Zamani, H. Safizadeh, "Improved Predictability, Timing Yield and Power Consumption Using Hierarchical Highways-on-Chip Planning Methodology", Integration-The Vlsi Journal, 2012 Jan vol. 44, no. 2, pp.123-135, 2012.

M. Saeedi, M. Arabzadeh, M. Saheb Zamani, M. Sedighi, "Block-Based Quantum-Logic Synthesis", Quantum Information and Computation, 2011 Mar vol. 11, no. 0, pp.262-277, 2011.

H. Ebrahimi, M. Saheb Zamani, H.R. Zarandi, "Mitigating Soft Errors in SRAM-Based FPGAs by Decoding Configuration Bits in Switch Boxes", Microelectronics Journal, 2011 Jan vol. 42, no. 1, pp.12-20, 2011.

M. Saeedi, M. Saheb Zamani, M. Sedighi, Z. Sasanian, "Reversible Circuit Synthesis Using a Cycle-Based Approach", Acm Journal On Emerging Technologies In Computing Systems, 2010 Dec vol. 6, no. 4, , 2010.

Ali Jahanian, M. Saheb Zamani, "Early buffer planning with congestion control using buffer requirement map", Journal of Circuits Systems and Computers, 2010 Aug vol. 19, no. 5, pp.949-973, 2010.

N. Mohamadzade, M. Saheb Zamani, M. Sedighi, "Auxiliary Qubit Selection: A Physical Synthesis Technique for Quantum Circuits", Quantum Information Processing, 2010 Jun vol. 9, no. 6, pp.1-16, 2010.

Ali Jahanian, M. Saheb Zamani, "Higher Routability and Reduced Crosstalk Noise by Asynchronous Multiplexing of On-chip Interconnects", Scientia Iranica, 2010 Jun vol. 17, no. 1, pp.11-24, 2010.

N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Quantum Physical Synthesis:Improving Physical Design by Netlist Modifications", Microelectronics Journal, 2010 Mar vol. 41, no. 4, , 2010.

M. Saeedi, M. Sedighi, M. Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Synthesis", , 2009 Dec vol. , no. 0, , 2009.

M. Saeedi, N. Mohamadzade, M. Sedighi, M. Saheb Zamani, "Towards A Thorough Set of Metrics for Quantum Circuit Systhesis", International Journal of Physics, 2009 Feb vol. , no. 2, , 2009.

A. Valizadeh, M. Saheb Zamani, B. Sadeghiyan, F. Mehdipour, "A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms", Journal On Computer Science and Engineering, 2009 Feb vol. 5, no. 2, pp.9-15, 2009.

M. Saeedi, M. Sedighi, M. Saheb Zamani, "Synthesis of Reversible Circuits Using A Moving Forward Strategy", Ieice Electronics Express, 2008 Aug vol. , no. 17, , 2008.

H. Noori, F. Mehdipour, M. Saheb Zamani, "An Architecture Framework for an Adaptive Extensible Processor", Journal of Supercomputing, 2008 Aug vol. , no. 45, , 2008.

M. Saeedi, M. Saheb Zamani, "A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems", Microprocessors and Microsystems, 2008 Jun vol. , no. 32, , 2008.

A. Jahanian, M. Saheb Zamani, "Using metro-on-chip in physical design flow for congestion and routability improvement", Microelectronics Journal, 2008 Feb vol. , no. 39, , 2008.

F. Mehdipour, H. Noori, M. Saheb Zamani, "improving Performance and Energy Saving in a Reconfigurable Processor Via Accelerating Control Data Flow Graphs", Ieice Transactions On Information and Systems, 2007 Dec vol. , no. 12, , 2007.

M. Saeedi, M. Saheb Zamani, A. Jahanian, "Evaluation Prediction and Reduction of Routing Congestion", Microelectronics Journal, 2007 Aug vol. , no. 38, , 2007.

A. Jahanian, M. Saheb Zamani, "Metro-on-Chip:an Effecient Physical Design Technique for Congestion Reduction", Ieice Electronics Express, 2007 Aug vol. , no. 25, , 2007.

F. Mehdipour, M. Saheb Zamani, H. Ahmadifar, T. Murakami, "An Integrated Temporal Partitioning and Physical Design Framework for Real-Time Reconfigurable Systems", , 2006 Feb vol. , no. 5, , 2006.

F. Mehdipour, M. Saheb Zamani, M. Sedighi, "An Integrated Temporal Partitioning and Physical Design Framework for Static Compilation of Reconfigurable Computing Systems", Microprocessors and Microsystems, 2006 Jan vol. , no. 30, , 2006.

M. Saheb Zamani, "A specification-driven framework for the floorplanning and placement of hierarchical VLSI designs", , 2004 Sep vol. , no. 2, , 2004.

Taught Courses

Course title

Description

Headlines

Date

Logic Design

4051

Seminar

4051

VLSI Design Algorithms

آشنایی با مسائل مطرح در طراحی فیزیکی مدارهای VLSI و شناخت الگوریتمهای بهینهسازی جایابی (placement)، مسیریابی (routing) و طرح تراشه (chip planning).

4042

Digital Systems Design

کسب مهارت در طراحی، درستی سنجی و اشکال زدایی مدارها و سیستم های دیجیتال بزرگ، آشنایی با زبان های توصیف سخت افزار، کسب مهارت در استفاده از

4042

Seminar

4041

Logic Design

4041

Logic Circuits

4032