Programmable Digital Systems Design
- Classification of digital systems: full-custom, semi-custom and programmable logic, programmable devices (PLA, PAL, SPLD)
- Basic architecture of programmable logic devices (PLD): SPLD, CPLD and FPGA, applications and advantages, PLD market
- FPLDs vs. ASIC: advantages and disadvantages
- Design cycle, Hardware description languages: basic concepts, applications (documentation, modelling and design and verification), levels of abstraction
- Introduction to VHDL, basic constructs, structural description, hierarchical specification, design configuration
- Sequential vs. concurrent execution, Parametric description
- data types, arrays and records, Operators, functions and procedures, operator overloading
- Sequential constructs: process, procedure and function,
Sequential statements: signal assignment, if statement, case statement, for-loop, while-loop, wait, function/procedure call
- Process statement, communication among processes and architectures, variables vs. signals
textio package
Concurrent statements: signal assignment, process, function/procedure call, component instantiation, conditional signal assignment, selected signal assignment
- Design flow: system requirements specification, architectural design, device and package selection,
- Design flow (cont’ed) : pin assignment, board-level and chip-level design, implementation, verification and documentation
- Synthesizable constructs, statements, operators and data types, RTL specification: combinational circuits, storage elements, data path vs. control path
- RTL specification (cont’ed): FSM with one/two/three processes, state encoding methods (sequential, one-hot, two-hot, gray, Johnson) advantages and disadvantages
- RTL specification (cont’ed): safe FSM, resource sharing in FSM, synthesis tool report, output generation (combinational outputs, Medvedev model, registered outputs), synchronous vs. asynchronous preset/reset, synchronizer circuit
- Synthesis tools considerations: inferring FFs and latches, variables vs. signals
- Case study: Xilinx synthesis tool
- Embedded Systems and Hardware/Software Co-design: software vs. hardware implementation, H/S partitioning and co-design, co-design flow, soft vs. hard processor core, configuring processor, adding peripherals, choosing hardware/software interface, integration.
- Design techniques: design reuse and IP-based design, IP classification, hierarchical design, using primitives
- Design techniques: implementing complex computational operations with memories, implementing FSMs with memories or embedded processor
- Reducing design cycle time: hierarchical design, floorplanning
- Optimization techniques: area optimization
- Optimization techniques: speed optimization
- Optimization techniques: speed optimization (Contd)
- Optimization techniques: power optimization
- High-level design: specification and synthesis (C/C++ and Simulink)
- PLDs: programming technologies (SRAM, flash, anti-fuse): advantages and disadvantages
- PLDs: logic block architectures (LUT-based, MUX-based, PLA/PAL-based)
- PLDs: Interconnection architectures (island-style, hierarchical), IO blocks, gigabit transceivers
- PLDs: special-purpose blocks: DSP blocks, block memory vs. distributed memory, processor cores, clock management blocks
- Commercial PLDs: Cyclone and Stratix
- Commercial PLDs: Spartan and Virtex/Kintex